188 lines
5.4 KiB
C++
188 lines
5.4 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __EXETRACE_HH__
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#define __EXETRACE_HH__
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#include <fstream>
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#include <vector>
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#include "sim/host.hh"
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#include "cpu/inst_seq.hh" // for InstSeqNum
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/static_inst.hh"
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class BaseCPU;
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namespace Trace {
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class InstRecord : public Record
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{
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protected:
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typedef TheISA::IntRegFile IntRegFile;
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// The following fields are initialized by the constructor and
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// thus guaranteed to be valid.
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BaseCPU *cpu;
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// need to make this ref-counted so it doesn't go away before we
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// dump the record
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StaticInstPtr staticInst;
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Addr PC;
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bool misspeculating;
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unsigned thread;
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// The remaining fields are only valid for particular instruction
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// types (e.g, addresses for memory ops) or when particular
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// options are enabled (e.g., tracing full register contents).
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// Each data field has an associated valid flag to indicate
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// whether the data field is valid.
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Addr addr;
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bool addr_valid;
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union {
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uint64_t as_int;
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double as_double;
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} data;
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enum {
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DataInvalid = 0,
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DataInt8 = 1, // set to equal number of bytes
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DataInt16 = 2,
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DataInt32 = 4,
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DataInt64 = 8,
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DataDouble = 3
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} data_status;
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InstSeqNum fetch_seq;
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bool fetch_seq_valid;
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InstSeqNum cp_seq;
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bool cp_seq_valid;
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struct iRegFile {
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IntRegFile regs;
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};
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iRegFile *iregs;
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bool regs_valid;
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public:
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InstRecord(Tick _cycle, BaseCPU *_cpu,
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const StaticInstPtr &_staticInst,
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Addr _pc, bool spec, int _thread)
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: Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
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misspeculating(spec), thread(_thread)
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{
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data_status = DataInvalid;
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addr_valid = false;
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regs_valid = false;
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fetch_seq_valid = false;
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cp_seq_valid = false;
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}
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virtual ~InstRecord() { }
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virtual void dump(std::ostream &outs);
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void setAddr(Addr a) { addr = a; addr_valid = true; }
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void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
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void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
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void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
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void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
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void setData(int64_t d) { setData((uint64_t)d); }
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void setData(int32_t d) { setData((uint32_t)d); }
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void setData(int16_t d) { setData((uint16_t)d); }
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void setData(int8_t d) { setData((uint8_t)d); }
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void setData(double d) { data.as_double = d; data_status = DataDouble; }
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void setFetchSeq(InstSeqNum seq)
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{ fetch_seq = seq; fetch_seq_valid = true; }
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void setCPSeq(InstSeqNum seq)
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{ cp_seq = seq; cp_seq_valid = true; }
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void setRegs(const IntRegFile ®s);
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void finalize() { theLog.append(this); }
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enum InstExecFlagBits {
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TRACE_MISSPEC = 0,
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PRINT_CYCLE,
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PRINT_OP_CLASS,
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PRINT_THREAD_NUM,
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PRINT_RESULT_DATA,
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PRINT_EFF_ADDR,
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PRINT_INT_REGS,
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PRINT_FETCH_SEQ,
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PRINT_CP_SEQ,
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INTEL_FORMAT,
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NUM_BITS
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};
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static std::vector<bool> flags;
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static std::string trace_system;
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static void setParams();
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static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
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};
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inline void
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InstRecord::setRegs(const IntRegFile ®s)
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{
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if (!iregs)
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iregs = new iRegFile;
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memcpy(&iregs->regs, regs, sizeof(IntRegFile));
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regs_valid = true;
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}
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inline
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InstRecord *
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getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
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const StaticInstPtr staticInst,
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Addr pc, int thread = 0)
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{
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if (DTRACE(InstExec) &&
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(InstRecord::traceMisspec() || !xc->misspeculating())) {
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return new InstRecord(cycle, cpu, staticInst, pc,
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xc->misspeculating(), thread);
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}
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return NULL;
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}
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}
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#endif // __EXETRACE_HH__
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