530 lines
16 KiB
C++
530 lines
16 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_BASE_DYN_INST_HH__
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#define __CPU_BASE_DYN_INST_HH__
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#include <string>
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#include <vector>
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#include "base/fast_alloc.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/static_inst.hh"
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#include "encumbered/cpu/full/bpred_update.hh"
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#include "encumbered/cpu/full/op_class.hh"
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#include "encumbered/cpu/full/spec_memory.hh"
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#include "encumbered/cpu/full/spec_state.hh"
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#include "encumbered/mem/functional/main.hh"
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/**
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* @file
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* Defines a dynamic instruction context.
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*/
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// Forward declaration.
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class StaticInstPtr;
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template <class Impl>
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class BaseDynInst : public FastAlloc, public RefCounted
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{
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public:
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// Typedef for the CPU.
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typedef typename Impl::FullCPU FullCPU;
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/// Binary machine instruction type.
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typedef TheISA::MachInst MachInst;
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/// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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/// Integer register index type.
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typedef TheISA::IntReg IntReg;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
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};
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/** The static inst used by this dyn inst. */
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StaticInstPtr staticInst;
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////////////////////////////////////////////
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//
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// INSTRUCTION EXECUTION
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//
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////////////////////////////////////////////
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Trace::InstRecord *traceData;
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags,
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uint64_t *res);
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void prefetch(Addr addr, unsigned flags);
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void writeHint(Addr addr, int size, unsigned flags);
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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/** @todo: Consider making this private. */
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public:
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/** Is this instruction valid. */
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bool valid;
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/** The sequence number of the instruction. */
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InstSeqNum seqNum;
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/** How many source registers are ready. */
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unsigned readyRegs;
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/** Is the instruction completed. */
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bool completed;
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/** Can this instruction issue. */
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bool canIssue;
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/** Has this instruction issued. */
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bool issued;
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/** Has this instruction executed (or made it through execute) yet. */
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bool executed;
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/** Can this instruction commit. */
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bool canCommit;
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/** Is this instruction squashed. */
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bool squashed;
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/** Is this instruction squashed in the instruction queue. */
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bool squashedInIQ;
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/** Is this a recover instruction. */
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bool recoverInst;
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/** Is this a thread blocking instruction. */
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bool blockingInst; /* this inst has called thread_block() */
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/** Is this a thread syncrhonization instruction. */
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bool threadsyncWait;
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/** The thread this instruction is from. */
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short threadNumber;
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/** data address space ID, for loads & stores. */
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short asid;
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/** Pointer to the FullCPU object. */
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FullCPU *cpu;
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/** Pointer to the exec context. Will not exist in the final version. */
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ExecContext *xc;
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** The effective physical address. */
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Addr physEffAddr;
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/** Effective virtual address for a copy source. */
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Addr copySrcEffAddr;
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/** Effective physical address for a copy source. */
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Addr copySrcPhysEffAddr;
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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/** The size of the data to be stored. */
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int storeSize;
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/** The data to be stored. */
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IntReg storeData;
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union Result {
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uint64_t integer;
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float fp;
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double dbl;
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};
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/** The result of the instruction; assumes for now that there's only one
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* destination register.
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*/
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Result instResult;
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/** PC of this instruction. */
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Addr PC;
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/** Next non-speculative PC. It is not filled in at fetch, but rather
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* once the target of the branch is truly known (either decode or
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* execute).
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*/
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Addr nextPC;
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/** Predicted next PC. */
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Addr predPC;
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/** Count of total number of dynamic instructions. */
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static int instcount;
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/** Whether or not the source register is ready. Not sure this should be
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* here vs. the derived class.
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*/
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bool _readySrcRegIdx[MaxInstSrcRegs];
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public:
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/** BaseDynInst constructor given a binary instruction. */
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BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
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FullCPU *cpu);
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/** BaseDynInst constructor given a static inst pointer. */
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BaseDynInst(StaticInstPtr &_staticInst);
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/** BaseDynInst destructor. */
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~BaseDynInst();
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private:
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/** Function to initialize variables in the constructors. */
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void initVars();
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public:
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void
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trace_mem(Fault fault, // last fault
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MemCmd cmd, // last command
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Addr addr, // virtual address of access
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void *p, // memory accessed
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int nbytes); // access size
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/** Dumps out contents of this BaseDynInst. */
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void dump();
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/** Dumps out contents of this BaseDynInst into given string. */
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void dump(std::string &outstring);
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/** Returns the fault type. */
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Fault getFault() { return fault; }
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/** Checks whether or not this instruction has had its branch target
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* calculated yet. For now it is not utilized and is hacked to be
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* always false.
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*/
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bool doneTargCalc() { return false; }
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/** Returns the next PC. This could be the speculative next PC if it is
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* called prior to the actual branch target being calculated.
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*/
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Addr readNextPC() { return nextPC; }
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/** Set the predicted target of this current instruction. */
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void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
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/** Returns the predicted target of the branch. */
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Addr readPredTarg() { return predPC; }
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/** Returns whether the instruction was predicted taken or not. */
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bool predTaken() {
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return( predPC != (PC + sizeof(MachInst) ) );
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}
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/** Returns whether the instruction mispredicted. */
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bool mispredicted() { return (predPC != nextPC); }
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//
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// Instruction types. Forward checks to StaticInst object.
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//
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bool isNop() const { return staticInst->isNop(); }
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bool isMemRef() const { return staticInst->isMemRef(); }
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bool isLoad() const { return staticInst->isLoad(); }
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bool isStore() const { return staticInst->isStore(); }
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bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
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bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
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bool isCopy() const { return staticInst->isCopy(); }
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bool isInteger() const { return staticInst->isInteger(); }
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bool isFloating() const { return staticInst->isFloating(); }
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bool isControl() const { return staticInst->isControl(); }
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bool isCall() const { return staticInst->isCall(); }
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bool isReturn() const { return staticInst->isReturn(); }
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bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
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bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
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bool isCondCtrl() const { return staticInst->isCondCtrl(); }
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bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
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bool isThreadSync() const { return staticInst->isThreadSync(); }
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bool isSerializing() const { return staticInst->isSerializing(); }
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bool isMemBarrier() const { return staticInst->isMemBarrier(); }
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bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
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bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
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/** Returns the opclass of this instruction. */
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OpClass opClass() const { return staticInst->opClass(); }
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/** Returns the branch target address. */
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Addr branchTarget() const { return staticInst->branchTarget(PC); }
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/** Number of source registers. */
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int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
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/** Number of destination registers. */
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int8_t numDestRegs() const { return staticInst->numDestRegs(); }
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// the following are used to track physical register usage
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// for machines with separate int & FP reg files
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int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
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int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
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/** Returns the logical register index of the i'th destination register. */
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RegIndex destRegIdx(int i) const
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{
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return staticInst->destRegIdx(i);
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}
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/** Returns the logical register index of the i'th source register. */
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RegIndex srcRegIdx(int i) const
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{
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return staticInst->srcRegIdx(i);
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}
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/** Returns the result of an integer instruction. */
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uint64_t readIntResult() { return instResult.integer; }
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/** Returns the result of a floating point instruction. */
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float readFloatResult() { return instResult.fp; }
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/** Returns the result of a floating point (double) instruction. */
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double readDoubleResult() { return instResult.dbl; }
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//Push to .cc file.
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/** Records that one of the source registers is ready. */
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void markSrcRegReady()
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{
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++readyRegs;
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if(readyRegs == numSrcRegs()) {
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canIssue = true;
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}
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}
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/** Marks a specific register as ready.
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* @todo: Move this to .cc file.
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*/
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void markSrcRegReady(RegIndex src_idx)
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{
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++readyRegs;
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_readySrcRegIdx[src_idx] = 1;
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if(readyRegs == numSrcRegs()) {
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canIssue = true;
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}
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}
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/** Returns if a source register is ready. */
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bool isReadySrcRegIdx(int idx) const
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{
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return this->_readySrcRegIdx[idx];
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}
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/** Sets this instruction as completed. */
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void setCompleted() { completed = true; }
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/** Returns whethe or not this instruction is completed. */
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bool isCompleted() const { return completed; }
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/** Sets this instruction as ready to issue. */
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void setCanIssue() { canIssue = true; }
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/** Returns whether or not this instruction is ready to issue. */
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bool readyToIssue() const { return canIssue; }
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/** Sets this instruction as issued from the IQ. */
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void setIssued() { issued = true; }
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/** Returns whether or not this instruction has issued. */
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bool isIssued() const { return issued; }
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/** Sets this instruction as executed. */
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void setExecuted() { executed = true; }
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/** Returns whether or not this instruction has executed. */
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bool isExecuted() const { return executed; }
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/** Sets this instruction as ready to commit. */
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void setCanCommit() { canCommit = true; }
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/** Clears this instruction as being ready to commit. */
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void clearCanCommit() { canCommit = false; }
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/** Returns whether or not this instruction is ready to commit. */
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bool readyToCommit() const { return canCommit; }
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/** Sets this instruction as squashed. */
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void setSquashed() { squashed = true; }
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/** Returns whether or not this instruction is squashed. */
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bool isSquashed() const { return squashed; }
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/** Sets this instruction as squashed in the IQ. */
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void setSquashedInIQ() { squashedInIQ = true; }
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/** Returns whether or not this instruction is squashed in the IQ. */
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bool isSquashedInIQ() const { return squashedInIQ; }
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/** Read the PC of this instruction. */
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const Addr readPC() const { return PC; }
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/** Set the next PC of this instruction (its actual target). */
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void setNextPC(uint64_t val) { nextPC = val; }
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/** Returns the exec context.
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* @todo: Remove this once the ExecContext is no longer used.
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*/
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ExecContext *xcBase() { return xc; }
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private:
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/** Instruction effective address.
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* @todo: Consider if this is necessary or not.
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*/
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Addr instEffAddr;
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/** Whether or not the effective address calculation is completed.
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* @todo: Consider if this is necessary or not.
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*/
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bool eaCalcDone;
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public:
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/** Sets the effective address. */
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void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
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/** Returns the effective address. */
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const Addr &getEA() const { return instEffAddr; }
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/** Returns whether or not the eff. addr. calculation has been completed. */
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bool doneEACalc() { return eaCalcDone; }
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/** Returns whether or not the eff. addr. source registers are ready. */
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bool eaSrcsReady();
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public:
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/** Load queue index. */
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int16_t lqIdx;
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/** Store queue index. */
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int16_t sqIdx;
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};
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template<class Impl>
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template<class T>
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inline Fault
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BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
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{
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MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
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req->asid = asid;
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fault = cpu->translateDataReadReq(req);
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// Record key MemReq parameters so we can generate another one
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// just like it for the timing access without calling translate()
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// again (which might mess up the TLB).
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// Do I ever really need this? -KTL 3/05
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effAddr = req->vaddr;
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physEffAddr = req->paddr;
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memReqFlags = req->flags;
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/**
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* @todo
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* Replace the disjoint functional memory with a unified one and remove
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* this hack.
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*/
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#if !FULL_SYSTEM
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req->paddr = req->vaddr;
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#endif
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if (fault == NoFault) {
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fault = cpu->read(req, data, lqIdx);
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} else {
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// Return a fixed value to keep simulation deterministic even
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// along misspeculated paths.
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data = (T)-1;
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}
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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return fault;
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}
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template<class Impl>
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template<class T>
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inline Fault
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BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
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req->asid = asid;
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fault = cpu->translateDataWriteReq(req);
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// Record key MemReq parameters so we can generate another one
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// just like it for the timing access without calling translate()
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// again (which might mess up the TLB).
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effAddr = req->vaddr;
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physEffAddr = req->paddr;
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memReqFlags = req->flags;
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/**
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* @todo
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* Replace the disjoint functional memory with a unified one and remove
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* this hack.
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*/
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#if !FULL_SYSTEM
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req->paddr = req->vaddr;
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#endif
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if (fault == NoFault) {
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fault = cpu->write(req, data, sqIdx);
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}
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if (res) {
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// always return some result to keep misspeculated paths
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// (which will ignore faults) deterministic
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*res = (fault == NoFault) ? req->result : 0;
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}
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return fault;
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}
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#endif // __CPU_BASE_DYN_INST_HH__
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