814 lines
93 KiB
Text
814 lines
93 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.387282 # Number of seconds simulated
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sim_ticks 387281648500 # Number of ticks simulated
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final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 171377 # Simulator instruction rate (inst/s)
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host_op_rate 171918 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 47367883 # Simulator tick rate (ticks/s)
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host_mem_usage 224920 # Number of bytes of host memory used
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host_seconds 8176.04 # Real time elapsed on the host
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sim_insts 1401188945 # Number of instructions simulated
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sim_ops 1405604139 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
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system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 27424 # Total number of read requests seen
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system.physmem.writeReqs 2533 # Total number of write requests seen
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system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1755072 # Total number of bytes read from memory
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system.physmem.bytesWritten 162112 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 166 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 155 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 153 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 157 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 387281620500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 27424 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 2533 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 722664308 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests
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system.physmem.totBusLat 109696000 # Total cycles spent in databus access
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system.physmem.totBankLat 571816000 # Total cycles spent in bank access
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system.physmem.avgQLat 26351.53 # Average queueing delay per request
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system.physmem.avgBankLat 20850.93 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 51202.46 # Average memory access latency
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system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.00 # Average read queue length over time
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system.physmem.avgWrQLen 17.43 # Average write queue length over time
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system.physmem.readRowHits 18322 # Number of row buffer hits during reads
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system.physmem.writeRowHits 1102 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes
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system.physmem.avgGap 12927917.36 # Average gap between requests
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system.cpu.workload.num_syscalls 49 # Number of system calls
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system.cpu.numCycles 774563298 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued
|
|
system.cpu.iq.rate 1.884063 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 93686401 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 89037548 # Number of branches executed
|
|
system.cpu.iew.exec_stores 170451275 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.877200 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1153420359 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 569360985 # Number of memory references committed
|
|
system.cpu.commit.loads 402512843 # Number of loads committed
|
|
system.cpu.commit.membars 51356 # Number of memory barriers committed
|
|
system.cpu.commit.branches 86248928 # Number of branches committed
|
|
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 2295688996 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 3234318218 # The number of ROB writes
|
|
system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
|
|
system.cpu.icache.replacements 190 # number of replacements
|
|
system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 161931728 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 161931728 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1933 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1933 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1933 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1933 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1933 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1933 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 80019500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 80019500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 80019500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 80019500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41396.533885 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 41396.533885 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 41396.533885 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 41396.533885 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 32.250000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 601 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 601 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 601 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 601 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 601 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1332 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1332 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1332 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1332 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1332 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1332 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58461000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 58461000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58461000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 58461000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58461000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 58461000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43889.639640 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43889.639640 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 2556 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22450.499541 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 550174 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 24271 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 22.667958 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 20742.731551 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 1060.708507 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 647.059483 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.633018 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.032370 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.019747 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.685135 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 134 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 196304 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 196438 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 443776 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 443776 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 240583 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 240583 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 134 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 436887 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 437021 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 134 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 436887 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 437021 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1198 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4435 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 5633 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1198 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 26226 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 27424 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1198 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 26226 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 27424 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55773000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 468174000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 523947000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1550343500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1550343500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 55773000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2018517500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 2074290500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 55773000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2018517500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 2074290500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1332 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 200739 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 202071 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 443776 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 443776 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 262374 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 262374 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1332 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 463113 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 464445 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1332 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 463113 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 464445 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.899399 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022093 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.027876 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083053 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083053 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899399 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.056630 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.059047 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899399 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.056630 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.059047 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46555.091820 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 105563.472379 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 93013.846973 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71146.046533 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71146.046533 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46555.091820 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76966.273927 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 75637.780776 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46555.091820 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76966.273927 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 75637.780776 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 2533 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1198 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5633 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1198 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 27424 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1198 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 27424 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40693954 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 412667734 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 453361688 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1276994111 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1276994111 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40693954 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689661845 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1730355799 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40693954 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689661845 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1730355799 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022093 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027876 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083053 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083053 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056630 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059047 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056630 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059047 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33968.242070 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93047.967080 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80483.168472 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58601.904961 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58601.904961 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33968.242070 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64426.974949 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63096.404573 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33968.242070 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64426.974949 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63096.404573 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 459017 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4093.828969 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 365038721 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 463113 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 788.228188 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 342772000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 365037402 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses
|
|
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
|
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2818397 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles
|
|
system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles
|
|
system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
|
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 443776 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
|
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|