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gem5/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
Andreas Hansson b63631536d stats: Cumulative stats update 
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00

778 lines
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---------- Begin Simulation Statistics ----------
sim_seconds 0.043769 # Number of seconds simulated
sim_ticks 43769191000 # Number of ticks simulated
final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 69144 # Simulator instruction rate (inst/s)
host_op_rate 69144 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34257993 # Simulator tick rate (ticks/s)
host_mem_usage 232832 # Number of bytes of host memory used
host_seconds 1277.63 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 10592960 # Total number of bytes read from memory
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 43769170000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 165515 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 113997 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation
system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests
system.physmem.totBusLat 827575000 # Total cycles spent in databus access
system.physmem.totBankLat 1658222500 # Total cycles spent in bank access
system.physmem.avgQLat 37986.22 # Average queueing delay per request
system.physmem.avgBankLat 10018.56 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 53004.78 # Average memory access latency
system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.19 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.20 # Average read queue length over time
system.physmem.avgWrQLen 10.49 # Average write queue length over time
system.physmem.readRowHits 153779 # Number of row buffer hits during reads
system.physmem.writeRowHits 76898 # Number of row buffer hits during writes
system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes
system.physmem.avgGap 156591.38 # Average gap between requests
system.membus.throughput 408706846 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 34625 # Transaction distribution
system.membus.trans_dist::ReadResp 34625 # Transaction distribution
system.membus.trans_dist::Writeback 113997 # Transaction distribution
system.membus.trans_dist::ReadExReq 130890 # Transaction distribution
system.membus.trans_dist::ReadExResp 130890 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 17888768 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
system.cpu.branchPred.lookups 18742730 # Number of BP lookups
system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups
system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277790 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367938 # DTB read accesses
system.cpu.dtb.write_hits 14728966 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14736218 # DTB write accesses
system.cpu.dtb.data_hits 35006756 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35104156 # DTB accesses
system.cpu.itb.fetch_hits 12367759 # ITB hits
system.cpu.itb.fetch_misses 11021 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12378780 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 87538383 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35060070 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed.
system.cpu.activity 79.479981 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comNops 8748916 # Number of Nop instructions committed
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads
system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 84371 # number of replacements
system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits
system.cpu.icache.overall_hits::total 12250515 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses
system.cpu.icache.overall_misses::total 117235 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1462353516 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1462353516 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 131591 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits
system.cpu.l2cache.overall_hits::total 125249 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 130890 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130890 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 7103 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 165515 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
system.cpu.l2cache.overall_misses::total 165515 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 580141750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2014348750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2594490500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13747919500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 13747919500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 580141750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 15762268250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16342410000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 580141750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 15762268250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16342410000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81675.594819 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73190.493060 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74931.133574 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105034.146994 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105034.146994 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 98736.730810 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 98736.730810 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27522 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 34625 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130890 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130890 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7103 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165515 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 490395250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665695250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156090500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12145170500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12145170500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 490395250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13810865750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14301261000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 490395250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13810865750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14301261000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69040.581444 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60522.318509 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62269.761733 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92789.139736 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92789.139736 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 200251 # number of replacements
system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits
system.cpu.dcache.overall_hits::total 33754840 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses
system.cpu.dcache.overall_misses::total 1135175 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks
system.cpu.dcache.writebacks::total 168352 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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