6eb434c8a2
Cleaning up dead code. The CLREX stores zero directly to MISCREG_LOCKFLAG and so the request flag is no longer needed. The corresponding functionality in the cache tags is also removed.
660 lines
20 KiB
C++
660 lines
20 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Steve Reinhardt
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* Ali Saidi
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*/
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/**
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* @file
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* Declaration of a request, the overall memory request consisting of
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the parts of the request that are persistent throughout the transaction.
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*/
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#ifndef __MEM_REQUEST_HH__
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#define __MEM_REQUEST_HH__
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#include <cassert>
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#include <climits>
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#include "base/flags.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "sim/core.hh"
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/**
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* Special TaskIds that are used for per-context-switch stats dumps
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* and Cache Occupancy. Having too many tasks seems to be a problem
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* with vector stats. 1024 seems to be a reasonable number that
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* doesn't cause a problem with stats and is large enough to realistic
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* benchmarks (Linux/Android boot, BBench, etc.)
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*/
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namespace ContextSwitchTaskId {
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enum TaskId {
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MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
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Prefetcher = 1022, /* For cache lines brought in by prefetcher */
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DMA = 1023, /* Mostly Table Walker */
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Unknown = 1024,
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NumTaskId
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};
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}
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class Request;
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typedef Request* RequestPtr;
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typedef uint16_t MasterID;
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class Request
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{
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public:
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typedef uint32_t FlagsType;
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typedef uint8_t ArchFlagsType;
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typedef ::Flags<FlagsType> Flags;
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enum : FlagsType {
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/**
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* Architecture specific flags.
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*
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* These bits int the flag field are reserved for
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* architecture-specific code. For example, SPARC uses them to
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* represent ASIs.
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*/
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ARCH_BITS = 0x000000FF,
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/** The request was an instruction fetch. */
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INST_FETCH = 0x00000100,
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/** The virtual address is also the physical address. */
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PHYSICAL = 0x00000200,
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/**
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* The request is to an uncacheable address.
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*
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* @note Uncacheable accesses may be reordered by CPU models. The
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* STRICT_ORDER flag should be set if such reordering is
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* undesirable.
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*/
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UNCACHEABLE = 0x00000400,
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/**
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* The request is required to be strictly ordered by <i>CPU
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* models</i> and is non-speculative.
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*
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* A strictly ordered request is guaranteed to never be
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* re-ordered or executed speculatively by a CPU model. The
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* memory system may still reorder requests in caches unless
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* the UNCACHEABLE flag is set as well.
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*/
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STRICT_ORDER = 0x00000800,
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/** This request is to a memory mapped register. */
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MMAPPED_IPR = 0x00002000,
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/** This request is made in privileged mode. */
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PRIVILEGED = 0x00008000,
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/**
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* This is a write that is targeted and zeroing an entire
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* cache block. There is no need for a read/modify/write
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*/
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CACHE_BLOCK_ZERO = 0x00010000,
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/** The request should not cause a memory access. */
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NO_ACCESS = 0x00080000,
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/**
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* This request will lock or unlock the accessed memory. When
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* used with a load, the access locks the particular chunk of
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* memory. When used with a store, it unlocks. The rule is
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* that locked accesses have to be made up of a locked load,
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* some operation on the data, and then a locked store.
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*/
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LOCKED_RMW = 0x00100000,
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/** The request is a Load locked/store conditional. */
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LLSC = 0x00200000,
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/** This request is for a memory swap. */
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MEM_SWAP = 0x00400000,
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MEM_SWAP_COND = 0x00800000,
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/** The request is a prefetch. */
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PREFETCH = 0x01000000,
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/** The request should be prefetched into the exclusive state. */
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PF_EXCLUSIVE = 0x02000000,
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/** The request should be marked as LRU. */
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EVICT_NEXT = 0x04000000,
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/**
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* The request should be handled by the generic IPR code (only
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* valid together with MMAPPED_IPR)
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*/
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GENERIC_IPR = 0x08000000,
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/** The request targets the secure memory space. */
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SECURE = 0x10000000,
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/** The request is a page table walk */
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PT_WALK = 0x20000000,
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/**
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* These flags are *not* cleared when a Request object is
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* reused (assigned a new address).
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*/
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STICKY_FLAGS = INST_FETCH
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};
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/** Master Ids that are statically allocated
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* @{*/
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enum : MasterID {
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/** This master id is used for writeback requests by the caches */
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wbMasterId = 0,
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/**
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* This master id is used for functional requests that
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* don't come from a particular device
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*/
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funcMasterId = 1,
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/** This master id is used for message signaled interrupts */
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intMasterId = 2,
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/**
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* Invalid master id for assertion checking only. It is
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* invalid behavior to ever send this id as part of a request.
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*/
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invldMasterId = std::numeric_limits<MasterID>::max()
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};
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/** @} */
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private:
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typedef uint8_t PrivateFlagsType;
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typedef ::Flags<PrivateFlagsType> PrivateFlags;
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enum : PrivateFlagsType {
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/** Whether or not the size is valid. */
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VALID_SIZE = 0x00000001,
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/** Whether or not paddr is valid (has been written yet). */
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VALID_PADDR = 0x00000002,
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/** Whether or not the vaddr & asid are valid. */
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VALID_VADDR = 0x00000004,
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/** Whether or not the pc is valid. */
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VALID_PC = 0x00000010,
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/** Whether or not the context ID is valid. */
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VALID_CONTEXT_ID = 0x00000020,
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VALID_THREAD_ID = 0x00000040,
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/** Whether or not the sc result is valid. */
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VALID_EXTRA_DATA = 0x00000080,
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/**
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* These flags are *not* cleared when a Request object is reused
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* (assigned a new address).
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*/
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STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID | VALID_THREAD_ID
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};
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private:
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/**
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* Set up a physical (e.g. device) request in a previously
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* allocated Request object.
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*/
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void
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setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
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{
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assert(size >= 0);
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_paddr = paddr;
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_size = size;
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_time = time;
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_masterId = mid;
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_flags.clear(~STICKY_FLAGS);
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_flags.set(flags);
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privateFlags.clear(~STICKY_PRIVATE_FLAGS);
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privateFlags.set(VALID_PADDR|VALID_SIZE);
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depth = 0;
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accessDelta = 0;
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//translateDelta = 0;
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}
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/**
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* The physical address of the request. Valid only if validPaddr
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* is set.
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*/
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Addr _paddr;
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/**
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* The size of the request. This field must be set when vaddr or
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* paddr is written via setVirt() or setPhys(), so it is always
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* valid as long as one of the address fields is valid.
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*/
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unsigned _size;
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/** The requestor ID which is unique in the system for all ports
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* that are capable of issuing a transaction
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*/
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MasterID _masterId;
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/** Flag structure for the request. */
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Flags _flags;
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/** Private flags for field validity checking. */
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PrivateFlags privateFlags;
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/**
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* The time this request was started. Used to calculate
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* latencies. This field is set to curTick() any time paddr or vaddr
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* is written.
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*/
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Tick _time;
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/**
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* The task id associated with this request
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*/
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uint32_t _taskId;
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/** The address space ID. */
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int _asid;
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/** The virtual address of the request. */
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Addr _vaddr;
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/**
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* Extra data for the request, such as the return value of
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* store conditional or the compare value for a CAS. */
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uint64_t _extraData;
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/** The context ID (for statistics, typically). */
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ContextID _contextId;
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/** The thread ID (id within this CPU) */
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ThreadID _threadId;
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/** program counter of initiating access; for tracing/debugging */
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Addr _pc;
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public:
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/**
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* Minimal constructor. No fields are initialized. (Note that
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* _flags and privateFlags are cleared by Flags default
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* constructor.)
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*/
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Request()
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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translateDelta(0), accessDelta(0), depth(0)
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{}
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/**
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* Constructor for physical (e.g. device) requests. Initializes
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* just physical address, size, flags, and timestamp (to curTick()).
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* These fields are adequate to perform a request.
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*/
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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translateDelta(0), accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, curTick());
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}
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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translateDelta(0), accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, time);
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}
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Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
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Addr pc)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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translateDelta(0), accessDelta(0), depth(0)
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{
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setPhys(paddr, size, flags, mid, time);
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privateFlags.set(VALID_PC);
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_pc = pc;
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}
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Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
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Addr pc, ContextID cid, ThreadID tid)
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: _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
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_taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
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_extraData(0), _contextId(0), _threadId(0), _pc(0),
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translateDelta(0), accessDelta(0), depth(0)
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{
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setVirt(asid, vaddr, size, flags, mid, pc);
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setThreadContext(cid, tid);
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}
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~Request() {}
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/**
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* Set up CPU and thread numbers.
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*/
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void
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setThreadContext(ContextID context_id, ThreadID tid)
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{
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_contextId = context_id;
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_threadId = tid;
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privateFlags.set(VALID_CONTEXT_ID|VALID_THREAD_ID);
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}
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/**
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* Set up a virtual (e.g., CPU) request in a previously
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* allocated Request object.
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*/
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void
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setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
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Addr pc)
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{
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_asid = asid;
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_vaddr = vaddr;
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_size = size;
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_masterId = mid;
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_pc = pc;
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_time = curTick();
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_flags.clear(~STICKY_FLAGS);
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_flags.set(flags);
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privateFlags.clear(~STICKY_PRIVATE_FLAGS);
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privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
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depth = 0;
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accessDelta = 0;
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translateDelta = 0;
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}
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/**
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* Set just the physical address. This usually used to record the
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* result of a translation. However, when using virtualized CPUs
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* setPhys() is sometimes called to finalize a physical address
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* without a virtual address, so we can't check if the virtual
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* address is valid.
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*/
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void
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setPaddr(Addr paddr)
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{
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_paddr = paddr;
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privateFlags.set(VALID_PADDR);
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}
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/**
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* Generate two requests as if this request had been split into two
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* pieces. The original request can't have been translated already.
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*/
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void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
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{
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assert(privateFlags.isSet(VALID_VADDR));
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assert(privateFlags.noneSet(VALID_PADDR));
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assert(split_addr > _vaddr && split_addr < _vaddr + _size);
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req1 = new Request(*this);
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req2 = new Request(*this);
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req1->_size = split_addr - _vaddr;
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req2->_vaddr = split_addr;
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req2->_size = _size - req1->_size;
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}
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/**
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* Accessor for paddr.
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*/
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bool
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hasPaddr() const
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{
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return privateFlags.isSet(VALID_PADDR);
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}
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Addr
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getPaddr() const
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{
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assert(privateFlags.isSet(VALID_PADDR));
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return _paddr;
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}
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/**
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* Time for the TLB/table walker to successfully translate this request.
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*/
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Tick translateDelta;
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/**
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* Access latency to complete this memory transaction not including
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* translation time.
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*/
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Tick accessDelta;
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/**
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* Level of the cache hierachy where this request was responded to
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* (e.g. 0 = L1; 1 = L2).
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*/
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mutable int depth;
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/**
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* Accessor for size.
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*/
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bool
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hasSize() const
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{
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return privateFlags.isSet(VALID_SIZE);
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}
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unsigned
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getSize() const
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{
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assert(privateFlags.isSet(VALID_SIZE));
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return _size;
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}
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/** Accessor for time. */
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Tick
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time() const
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{
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assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
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return _time;
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}
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/** Accessor for flags. */
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Flags
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getFlags()
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{
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assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
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return _flags;
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}
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/** Note that unlike other accessors, this function sets *specific
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flags* (ORs them in); it does not assign its argument to the
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_flags field. Thus this method should rightly be called
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setFlags() and not just flags(). */
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void
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setFlags(Flags flags)
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{
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assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
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_flags.set(flags);
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}
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/** Accessor function for vaddr.*/
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bool
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hasVaddr() const
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{
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return privateFlags.isSet(VALID_VADDR);
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}
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Addr
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getVaddr() const
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{
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assert(privateFlags.isSet(VALID_VADDR));
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return _vaddr;
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}
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/** Accesssor for the requestor id. */
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MasterID
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masterId() const
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{
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return _masterId;
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}
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uint32_t
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taskId() const
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{
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return _taskId;
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}
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void
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taskId(uint32_t id) {
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_taskId = id;
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}
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/** Accessor function for asid.*/
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int
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getAsid() const
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{
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assert(privateFlags.isSet(VALID_VADDR));
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return _asid;
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}
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/** Accessor function for asid.*/
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void
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setAsid(int asid)
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{
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_asid = asid;
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}
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|
|
/** Accessor function for architecture-specific flags.*/
|
|
ArchFlagsType
|
|
getArchFlags() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
|
|
return _flags & ARCH_BITS;
|
|
}
|
|
|
|
/** Accessor function to check if sc result is valid. */
|
|
bool
|
|
extraDataValid() const
|
|
{
|
|
return privateFlags.isSet(VALID_EXTRA_DATA);
|
|
}
|
|
|
|
/** Accessor function for store conditional return value.*/
|
|
uint64_t
|
|
getExtraData() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_EXTRA_DATA));
|
|
return _extraData;
|
|
}
|
|
|
|
/** Accessor function for store conditional return value.*/
|
|
void
|
|
setExtraData(uint64_t extraData)
|
|
{
|
|
_extraData = extraData;
|
|
privateFlags.set(VALID_EXTRA_DATA);
|
|
}
|
|
|
|
bool
|
|
hasContextId() const
|
|
{
|
|
return privateFlags.isSet(VALID_CONTEXT_ID);
|
|
}
|
|
|
|
/** Accessor function for context ID.*/
|
|
ContextID
|
|
contextId() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_CONTEXT_ID));
|
|
return _contextId;
|
|
}
|
|
|
|
/** Accessor function for thread ID. */
|
|
ThreadID
|
|
threadId() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_THREAD_ID));
|
|
return _threadId;
|
|
}
|
|
|
|
void
|
|
setPC(Addr pc)
|
|
{
|
|
privateFlags.set(VALID_PC);
|
|
_pc = pc;
|
|
}
|
|
|
|
bool
|
|
hasPC() const
|
|
{
|
|
return privateFlags.isSet(VALID_PC);
|
|
}
|
|
|
|
/** Accessor function for pc.*/
|
|
Addr
|
|
getPC() const
|
|
{
|
|
assert(privateFlags.isSet(VALID_PC));
|
|
return _pc;
|
|
}
|
|
|
|
/**
|
|
* Increment/Get the depth at which this request is responded to.
|
|
* This currently happens when the request misses in any cache level.
|
|
*/
|
|
void incAccessDepth() const { depth++; }
|
|
int getAccessDepth() const { return depth; }
|
|
|
|
/**
|
|
* Set/Get the time taken for this request to be successfully translated.
|
|
*/
|
|
void setTranslateLatency() { translateDelta = curTick() - _time; }
|
|
Tick getTranslateLatency() const { return translateDelta; }
|
|
|
|
/**
|
|
* Set/Get the time taken to complete this request's access, not including
|
|
* the time to successfully translate the request.
|
|
*/
|
|
void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
|
|
Tick getAccessLatency() const { return accessDelta; }
|
|
|
|
/** Accessor functions for flags. Note that these are for testing
|
|
only; setting flags should be done via setFlags(). */
|
|
bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
|
|
bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
|
|
bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
|
|
bool isPrefetch() const { return _flags.isSet(PREFETCH); }
|
|
bool isLLSC() const { return _flags.isSet(LLSC); }
|
|
bool isPriv() const { return _flags.isSet(PRIVILEGED); }
|
|
bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
|
|
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
|
|
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
|
|
bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
|
|
bool isSecure() const { return _flags.isSet(SECURE); }
|
|
bool isPTWalk() const { return _flags.isSet(PT_WALK); }
|
|
};
|
|
|
|
#endif // __MEM_REQUEST_HH__
|