c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
619 lines
70 KiB
Text
619 lines
70 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.829332 # Number of seconds simulated
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sim_ticks 1829331993500 # Number of ticks simulated
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final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2920462 # Simulator instruction rate (inst/s)
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host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 88984410684 # Simulator tick rate (ticks/s)
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host_mem_usage 366200 # Number of bytes of host memory used
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host_seconds 20.56 # Real time elapsed on the host
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sim_insts 60038469 # Number of instructions simulated
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sim_ops 60038469 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory
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system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory
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system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s)
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system.membus.trans_dist::ReadReq 948404 # Transaction distribution
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system.membus.trans_dist::ReadResp 948404 # Transaction distribution
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system.membus.trans_dist::WriteReq 9838 # Transaction distribution
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system.membus.trans_dist::WriteResp 9838 # Transaction distribution
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system.membus.trans_dist::Writeback 74279 # Transaction distribution
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system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
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system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
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system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
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system.membus.trans_dist::ReadExReq 116985 # Transaction distribution
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system.membus.trans_dist::ReadExResp 116985 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 1174168 # Request fanout histogram
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.snoop_fanout::total 1174168 # Request fanout histogram
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system.iocache.tags.replacements 41686 # number of replacements
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system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
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system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
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system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
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system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
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system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
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system.iocache.tags.tag_accesses 375534 # Number of tag accesses
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system.iocache.tags.data_accesses 375534 # Number of data accesses
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system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
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system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
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system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
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system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
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system.iocache.demand_misses::total 174 # number of demand (read+write) misses
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system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
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system.iocache.overall_misses::total 174 # number of overall misses
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system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
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system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
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system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
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system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
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system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
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system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
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system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.fast_writes 41552 # number of fast writes performed
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
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system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
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system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
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system.disk0.dma_write_txs 395 # Number of DMA write transactions.
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system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
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system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
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system.disk2.dma_write_txs 1 # Number of DMA write transactions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 9710423 # DTB read hits
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system.cpu.dtb.read_misses 10329 # DTB read misses
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system.cpu.dtb.read_acv 210 # DTB read access violations
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system.cpu.dtb.read_accesses 728856 # DTB read accesses
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system.cpu.dtb.write_hits 6352496 # DTB write hits
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system.cpu.dtb.write_misses 1142 # DTB write misses
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system.cpu.dtb.write_acv 157 # DTB write access violations
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system.cpu.dtb.write_accesses 291931 # DTB write accesses
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system.cpu.dtb.data_hits 16062919 # DTB hits
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system.cpu.dtb.data_misses 11471 # DTB misses
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system.cpu.dtb.data_acv 367 # DTB access violations
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system.cpu.dtb.data_accesses 1020787 # DTB accesses
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system.cpu.itb.fetch_hits 4974637 # ITB hits
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system.cpu.itb.fetch_misses 5006 # ITB misses
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system.cpu.itb.fetch_acv 184 # ITB acv
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system.cpu.itb.fetch_accesses 4979643 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.numCycles 3658670345 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 60038469 # Number of instructions committed
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system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
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system.cpu.num_func_calls 1484182 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
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system.cpu.num_int_insts 55913692 # number of integer instructions
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system.cpu.num_fp_insts 324460 # number of float instructions
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system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
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system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
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system.cpu.num_mem_refs 16115703 # number of memory refs
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system.cpu.num_load_insts 9747509 # Number of load instructions
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system.cpu.num_store_insts 6368194 # Number of store instructions
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system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
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system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
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system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
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system.cpu.Branches 9064428 # Number of branches fetched
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system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
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system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
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system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
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system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
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system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
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system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
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system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
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system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 60050307 # Class of executed instruction
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
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system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
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system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
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system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
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system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
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system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
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|
system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
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system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
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system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
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system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
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system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
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system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
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system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
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system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
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system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
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system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
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system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
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system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
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system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
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system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
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system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
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system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
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system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192179 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1908
|
|
system.cpu.kern.mode_good::user 1737
|
|
system.cpu.kern.mode_good::idle 171
|
|
system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 9838 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.icache.tags.replacements 919603 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 59130077 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 920230 # number of overall misses
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 992289 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 74279 # number of writebacks
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 2042707 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 833484 # number of writebacks
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram
|
|
|
|
---------- End Simulation Statistics ----------
|