a8fbc4ec76
arch/sparc/isa/decoder.isa:
Made sure if a register was assigned to along some control path, then all paths on which no exception would block commit set a value as well. Also, Rs1 is treated as signed for bpr instructions.
arch/sparc/isa/formats/integerop.isa:
Added an IntOpImm11 class which sign extends the SIMM11 immediate field.
arch/sparc/isa/formats/mem.isa:
Fixed how offsets are used, and how disassembly is generated.
arch/sparc/linux/process.cc:
Added fstat and exit_group syscalls.
--HG--
extra : convert_revision : 3b4427d239d254a92179a4137441125b8a364264
349 lines
11 KiB
Text
349 lines
11 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Integer operate instructions
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//
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output header {{
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/**
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* Base class for integer operations.
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*/
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class IntOp : public SparcStaticInst
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{
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protected:
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// Constructor
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IntOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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virtual bool printPseudoOps(std::ostream &os, Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Base class for immediate integer operations.
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*/
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class IntOpImm : public IntOp
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{
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protected:
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// Constructor
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IntOpImm(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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IntOp(mnem, _machInst, __opClass)
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{
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}
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int32_t imm;
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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virtual bool printPseudoOps(std::ostream &os, Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Base class for 10 bit immediate integer operations.
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*/
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class IntOpImm10 : public IntOpImm
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{
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protected:
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// Constructor
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IntOpImm10(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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IntOpImm(mnem, _machInst, __opClass)
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{
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imm = sign_ext(SIMM10, 10);
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}
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};
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/**
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* Base class for 11 bit immediate integer operations.
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*/
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class IntOpImm11 : public IntOpImm
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{
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protected:
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// Constructor
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IntOpImm11(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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IntOpImm(mnem, _machInst, __opClass)
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{
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imm = sign_ext(SIMM11, 11);
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}
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};
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/**
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* Base class for 13 bit immediate integer operations.
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*/
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class IntOpImm13 : public IntOpImm
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{
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protected:
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// Constructor
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IntOpImm13(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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IntOpImm(mnem, _machInst, __opClass)
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{
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imm = sign_ext(SIMM13, 13);
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}
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};
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/**
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* Base class for sethi.
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*/
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class SetHi : public IntOpImm
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{
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protected:
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// Constructor
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SetHi(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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IntOpImm(mnem, _machInst, __opClass)
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{
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imm = (IMM22 << 10) & 0xFFFFFC00;
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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}};
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def template SetHiDecode {{
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{
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if(RD == 0 && IMM22 == 0)
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return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
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else
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return (SparcStaticInst *)(new %(class_name)s(machInst));
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}
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}};
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output decoder {{
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bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
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const SymbolTable *symbab) const
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{
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if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
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{
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printMnemonic(os, "mov");
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if(_numSrcRegs > 0)
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printReg(os, _srcRegIdx[1]);
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ccprintf(os, ", ");
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if(_numDestRegs > 0)
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printReg(os, _destRegIdx[0]);
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return true;
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}
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return false;
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}
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bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
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const SymbolTable *symbab) const
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{
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if(!strcmp(mnemonic, "or"))
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{
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if(_srcRegIdx[0] == 0)
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{
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if(imm == 0)
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{
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printMnemonic(os, "clr");
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if(_numDestRegs > 0)
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printReg(os, _destRegIdx[0]);
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return true;
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}
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else
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{
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printMnemonic(os, "mov");
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ccprintf(os, ", 0x%x, ", imm);
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if(_numDestRegs > 0)
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printReg(os, _destRegIdx[0]);
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return true;
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}
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}
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else if(imm == 0)
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{
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printMnemonic(os, "mov");
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if(_numSrcRegs > 0)
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printReg(os, _srcRegIdx[0]);
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ccprintf(os, ", ");
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if(_numDestRegs > 0)
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printReg(os, _destRegIdx[0]);
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return true;
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}
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}
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return false;
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}
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std::string IntOp::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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if(!printPseudoOps(response, pc, symtab))
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{
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printMnemonic(response, mnemonic);
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if (_numSrcRegs > 0)
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{
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printReg(response, _srcRegIdx[0]);
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for(int x = 1; x < _numSrcRegs; x++)
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{
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response << ", ";
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printReg(response, _srcRegIdx[x]);
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}
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}
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if (_numDestRegs > 0)
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{
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if(_numSrcRegs > 0)
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response << ", ";
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printReg(response, _destRegIdx[0]);
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}
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}
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return response.str();
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}
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std::string IntOpImm::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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if(!printPseudoOps(response, pc, symtab))
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{
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printMnemonic(response, mnemonic);
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if (_numSrcRegs > 0)
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{
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printReg(response, _srcRegIdx[0]);
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for(int x = 1; x < _numSrcRegs - 1; x++)
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{
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response << ", ";
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printReg(response, _srcRegIdx[x]);
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}
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}
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if(_numSrcRegs > 0)
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response << ", ";
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ccprintf(response, "0x%x", imm);
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if (_numDestRegs > 0)
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{
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response << ", ";
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printReg(response, _destRegIdx[0]);
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}
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}
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return response.str();
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}
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std::string SetHi::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, mnemonic);
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if(_numSrcRegs > 0)
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response << ", ";
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ccprintf(response, "%%hi(0x%x), ", imm);
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printReg(response, _destRegIdx[0]);
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return response.str();
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}
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}};
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def template IntOpExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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//Write the resulting state to the execution context
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if(fault == NoFault)
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{
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%(cc_code)s;
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%(op_wb)s;
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}
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return fault;
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}
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}};
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let {{
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def doIntFormat(code, ccCode, name, Name, opt_flags):
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(usesImm, code, immCode,
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rString, iString) = splitOutImm(code)
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iop = InstObjParams(name, Name, 'IntOp', code,
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opt_flags, ("cc_code", ccCode))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = IntOpExecute.subst(iop)
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if usesImm:
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imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
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immCode, opt_flags, ("cc_code", ccCode))
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header_output += BasicDeclare.subst(imm_iop)
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decoder_output += BasicConstructor.subst(imm_iop)
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exec_output += IntOpExecute.subst(imm_iop)
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decode_block = ROrImmDecode.subst(iop)
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else:
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decode_block = BasicDecode.subst(iop)
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return (header_output, decoder_output, exec_output, decode_block)
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calcCcCode = '''
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CcrIccN = (Rd >> 31) & 1;
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CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
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CcrXccN = (Rd >> 63) & 1;
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CcrXccZ = (Rd == 0);
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CcrIccV = %(ivValue)s;
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CcrIccC = %(icValue)s;
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CcrXccV = %(xvValue)s;
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CcrXccC = %(xcValue)s;
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DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
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DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
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DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
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DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
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DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
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DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
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DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
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DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
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'''
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}};
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// Primary format for integer operate instructions:
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def format IntOp(code, *opt_flags) {{
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ccCode = ''
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doIntFormat(code, ccCode,
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name, Name, opt_flags)
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}};
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// Primary format for integer operate instructions:
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def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
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ccCode = calcCcCode % vars()
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doIntFormat(code, ccCode,
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name, Name, opt_flags)
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}};
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// Primary format for integer operate instructions:
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def format IntOpCcRes(code, *opt_flags) {{
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ccCode = calcCcCode % {"icValue":"0",
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"ivValue":"0",
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"xcValue":"0",
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"xvValue":"0"}
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doIntFormat(code, ccCode,
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name, Name, opt_flags)
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}};
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def format SetHi(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'SetHi',
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code, opt_flags, ("cc_code", ''))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = IntOpExecute.subst(iop)
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decode_block = SetHiDecode.subst(iop)
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}};
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