fce3433b2e
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
1150 lines
132 KiB
Text
1150 lines
132 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.854310 # Number of seconds simulated
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sim_ticks 1854309852000 # Number of ticks simulated
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final_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 117975 # Simulator instruction rate (inst/s)
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host_op_rate 117975 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4129044881 # Simulator tick rate (ticks/s)
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host_mem_usage 335500 # Number of bytes of host memory used
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host_seconds 449.09 # Real time elapsed on the host
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sim_insts 52981417 # Number of instructions simulated
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sim_ops 52981417 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28494848 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 445232 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 445232 # Total number of read requests seen
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system.physmem.writeReqs 117444 # Total number of write requests seen
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system.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 28494848 # Total number of bytes read from memory
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system.physmem.bytesWritten 7516416 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry
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system.physmem.totGap 1854304427000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 445232 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 119231 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 171 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 7898633503 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests
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system.physmem.totBusLat 2225860000 # Total cycles spent in databus access
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system.physmem.totBankLat 5511935000 # Total cycles spent in bank access
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system.physmem.avgQLat 17742.88 # Average queueing delay per request
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system.physmem.avgBankLat 12381.59 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 35124.47 # Average memory access latency
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system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.15 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 10.74 # Average write queue length over time
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system.physmem.readRowHits 417598 # Number of row buffer hits during reads
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system.physmem.writeRowHits 91555 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes
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system.physmem.avgGap 3295510.08 # Average gap between requests
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system.iocache.replacements 41685 # number of replacements
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system.iocache.tagsinuse 1.265033 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit.
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system.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor
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system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy
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system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy
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system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
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system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
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system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
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system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
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system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
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system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
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system.iocache.overall_misses::total 41725 # number of overall misses
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system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
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system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
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system.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles
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system.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles
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system.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles
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system.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles
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system.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles
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system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
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system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
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system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
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system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
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system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
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system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
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system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
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system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
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system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
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system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency
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system.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency
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system.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency
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system.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency
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system.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency
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system.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.cache_copies 0 # number of cache copies performed
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|
system.iocache.writebacks::writebacks 41512 # number of writebacks
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|
system.iocache.writebacks::total 41512 # number of writebacks
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system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
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system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
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system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
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system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
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system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 13854519 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5815567 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9921013 # DTB read hits
|
|
system.cpu.dtb.read_misses 41705 # DTB read misses
|
|
system.cpu.dtb.read_acv 547 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 941529 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6598119 # DTB write hits
|
|
system.cpu.dtb.write_misses 10489 # DTB write misses
|
|
system.cpu.dtb.write_acv 411 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 338424 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16519132 # DTB hits
|
|
system.cpu.dtb.data_misses 52194 # DTB misses
|
|
system.cpu.dtb.data_acv 958 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1279953 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1307587 # ITB hits
|
|
system.cpu.itb.fetch_misses 36909 # ITB misses
|
|
system.cpu.itb.fetch_acv 1032 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1344496 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 109625107 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 12111886 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 11346848 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 56823763 # Type of FU issued
|
|
system.cpu.iq.rate 0.518346 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 789067 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3527845 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 16614745 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 8928138 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6623837 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.514074 # Inst execution rate
|
|
system.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 55913848 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 27775021 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 37616621 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.510046 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56172173 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15470144 # Number of memory references committed
|
|
system.cpu.commit.loads 9092271 # Number of loads committed
|
|
system.cpu.commit.membars 226349 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8440686 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52021801 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740555 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 140883934 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 128542305 # The number of ROB writes
|
|
system.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52981417 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 52981417 # Number of Instructions Simulated
|
|
system.cpu.cpi 2.069124 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.483296 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 73895852 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 40324169 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 166027 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167433 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1987804 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu.icache.replacements 1009308 # number of replacements
|
|
system.cpu.icache.tagsinuse 510.238404 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 7486940 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1009816 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 7.414163 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 510.238404 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7486941 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7486941 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 7486941 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7486941 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 7486941 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7486941 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1065537 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1065537 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1065537 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1065537 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1065537 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1065537 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14679368493 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 14679368493 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 14679368493 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 14679368493 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 616 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 184 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 37.652174 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 308 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55502 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 55502 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 55502 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 55502 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 55502 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 55502 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010035 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1010035 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1010035 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1010035 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1010035 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1010035 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042197495 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12042197495 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042197495 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12042197495 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042197495 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12042197495 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118099 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.118099 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.118099 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.554659 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.554659 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 338291 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 65364.646667 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2546198 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 403460 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 6.310906 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 4180772752 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 54014.481347 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 5327.723075 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6022.442245 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.824196 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.081295 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.091895 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.997385 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 994848 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 827113 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1821961 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 840942 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 840942 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 185617 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 185617 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 994848 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1012730 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2007578 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 994848 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1012730 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2007578 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 15075 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 273765 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 288840 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115444 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 115444 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15075 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389209 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404284 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15075 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389209 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404284 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1040084000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12407885000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 13447969000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 291000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7693925000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7693925000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1040084000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 20101810000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 21141894000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1040084000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 20101810000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 21141894000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009923 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1100878 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2110801 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 840942 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 840942 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 301061 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 301061 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1009923 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1401939 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2411862 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1009923 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1401939 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2411862 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014927 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248679 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.136839 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.573770 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.573770 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383457 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383457 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014927 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277622 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.167623 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014927 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277622 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.167623 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68993.963516 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45323.123847 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46558.541061 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8314.285714 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8314.285714 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66646.382662 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66646.382662 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52294.659200 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52294.659200 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 75932 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 75932 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15074 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273765 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 288839 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115444 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115444 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15074 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389209 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404283 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15074 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389209 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404283 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 852119347 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058627177 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9910746524 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 507531 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 507531 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6283747927 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6283747927 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 852119347 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15342375104 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 16194494451 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 852119347 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15342375104 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 16194494451 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333816000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333816000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882705000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882705000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216521000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216521000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136839 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.573770 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.573770 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383457 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383457 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.167623 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.167623 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56529.079674 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.062433 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34312.355755 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14500.885714 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14500.885714 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54431.134810 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54431.134810 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1401345 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 11814052 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1401857 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 8.427430 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7207582 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7207582 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4204734 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4204734 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 185999 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 185999 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 11412316 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11412316 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 11412316 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11412316 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1803400 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1803400 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1942918 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1942918 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3746318 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3746318 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3746318 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3746318 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 34352879000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 34352879000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 65301849857 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 65301849857 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 305868500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 305868500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 99654728857 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 99654728857 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 99654728857 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 99654728857 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9010982 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9010982 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6147652 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6147652 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208748 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 208748 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15158634 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15158634 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15158634 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15158634 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200134 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.200134 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 840942 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 840942 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191983 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1908
|
|
system.cpu.kern.mode_good::user 1738
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|