2068 lines
245 KiB
Text
2068 lines
245 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.903873 # Number of seconds simulated
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sim_ticks 2903873346500 # Number of ticks simulated
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final_tick 2903873346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 443372 # Simulator instruction rate (inst/s)
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host_op_rate 534574 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 11447260542 # Simulator tick rate (ticks/s)
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host_mem_usage 578032 # Number of bytes of host memory used
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host_seconds 253.67 # Real time elapsed on the host
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sim_insts 112471852 # Number of instructions simulated
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sim_ops 135607518 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 555940 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4011424 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 630912 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 4981252 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10181128 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 555940 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 630912 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1186852 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7592512 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7610036 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 17140 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 63197 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 9858 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 77833 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 168053 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 118633 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 123014 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 191448 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1381405 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 110 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 217266 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 1715382 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3506051 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 191448 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 217266 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 408713 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2614615 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2620650 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2614615 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 191448 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1387437 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 110 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 217266 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 1715385 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6126701 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 168053 # Number of read requests accepted
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system.physmem.writeReqs 123014 # Number of write requests accepted
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system.physmem.readBursts 168053 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 123014 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 10747264 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7624000 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10181128 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7610036 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9950 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9635 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10758 # Per bank write bursts
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system.physmem.perBankRdBursts::3 10205 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18891 # Per bank write bursts
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system.physmem.perBankRdBursts::5 10113 # Per bank write bursts
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system.physmem.perBankRdBursts::6 10004 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10172 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9614 # Per bank write bursts
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system.physmem.perBankRdBursts::9 10312 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9759 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9150 # Per bank write bursts
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system.physmem.perBankRdBursts::12 10005 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10185 # Per bank write bursts
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system.physmem.perBankRdBursts::14 9904 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9269 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7437 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7207 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8535 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7773 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7341 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7352 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7319 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7510 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7314 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7939 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7417 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7018 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7499 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7483 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7310 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6671 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
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system.physmem.totGap 2903872984500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 9558 # Read request sizes (log2)
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system.physmem.readPktSize::3 14 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 158481 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4381 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 118633 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 167142 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 249 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 201 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 185 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 181 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 179 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 178 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 168 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 167 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 167 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 166 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3039 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5989 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5952 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6236 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5884 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 6356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6684 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 7266 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 7233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 8435 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7037 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6033 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 337 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 336 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 277 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 204 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 80 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 145 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::52 87 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 58 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 61 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 58746 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::mean 312.722568 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 182.930860 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 334.291475 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 21602 36.77% 36.77% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::128-255 14804 25.20% 61.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 5471 9.31% 71.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3214 5.47% 76.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2508 4.27% 81.03% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 1574 2.68% 83.70% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 969 1.65% 85.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1055 1.80% 87.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 7549 12.85% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 58746 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5821 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 28.848136 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 550.683804 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 5819 99.97% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
|
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system.physmem.rdPerTurnAround::total 5821 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5821 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 20.464697 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.574066 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 13.714843 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::0-3 19 0.33% 0.33% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::4-7 13 0.22% 0.55% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::8-11 4 0.07% 0.62% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::12-15 16 0.27% 0.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 4888 83.97% 84.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 79 1.36% 86.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 98 1.68% 87.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 80 1.37% 89.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 289 4.96% 94.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 57 0.98% 95.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 18 0.31% 95.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 15 0.26% 95.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 14 0.24% 96.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 4 0.07% 96.10% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 6 0.10% 96.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 3 0.05% 96.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 159 2.73% 98.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 4 0.07% 99.06% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 4 0.07% 99.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 2 0.03% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 6 0.10% 99.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 3 0.05% 99.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 2 0.03% 99.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.07% 99.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 6 0.10% 99.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 1 0.02% 99.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 12 0.21% 99.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 3 0.05% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 3 0.05% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5821 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1465999500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4614612000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 839630000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8730.03 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27480.03 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 12.35 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 138262 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 90042 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.59 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 9976647.94 # Average gap between requests
|
|
system.physmem.pageHitRate 79.53 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 228894120 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 124892625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 699878400 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 391871520 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 189666434880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 87151382055 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1665871386000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1944134739600 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 669.498637 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 2771164197500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 96966480000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 35735947500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 215225640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 117434625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 609936600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 380058480 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 189666434880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 85517443710 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1667304665250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1943811199185 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 669.387220 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 2773570809500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 96966480000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 33335958000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.bridge.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dtb.walker.walks 6853 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksShort 6853 # Table walker walks initiated with short descriptors
|
|
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2243 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 6853 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0 6853 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 6853 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::samples 5823 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::mean 12916.709600 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::gmean 11256.445833 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::stdev 6610.788578 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::0-8191 1557 26.74% 26.74% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::8192-16383 2962 50.87% 77.61% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1237 21.24% 98.85% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::24576-32767 65 1.12% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::81920-90111 2 0.03% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::total 5823 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 3601 61.84% 61.84% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::1M 2222 38.16% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 5823 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6853 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6853 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5823 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5823 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 12676 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 12198930 # DTB read hits
|
|
system.cpu0.dtb.read_misses 5954 # DTB read misses
|
|
system.cpu0.dtb.write_hits 9656685 # DTB write hits
|
|
system.cpu0.dtb.write_misses 899 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 4524 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 886 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 12204884 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 9657584 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 21855615 # DTB hits
|
|
system.cpu0.dtb.misses 6853 # DTB misses
|
|
system.cpu0.dtb.accesses 21862468 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.itb.walker.walks 3536 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksShort 3536 # Table walker walks initiated with short descriptors
|
|
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 846 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.itb.walker.walkWaitTime::samples 3536 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 3536 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 3536 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::samples 2700 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::mean 13506.851852 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::gmean 11618.794043 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::stdev 7003.469294 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::0-8191 708 26.22% 26.22% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1289 47.74% 73.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::16384-24575 690 25.56% 99.52% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::24576-32767 12 0.44% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::total 2700 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 1854 68.67% 68.67% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::1M 846 31.33% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 2700 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3536 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3536 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2700 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2700 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 6236 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 57475685 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3536 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 57479221 # ITB inst accesses
|
|
system.cpu0.itb.hits 57475685 # DTB hits
|
|
system.cpu0.itb.misses 3536 # DTB misses
|
|
system.cpu0.itb.accesses 57479221 # DTB accesses
|
|
system.cpu0.numPwrStateTransitions 3084 # Number of power state transitions
|
|
system.cpu0.pwrStateClkGateDist::samples 1542 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::mean 1561186798.199741 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::stdev 23928880440.151150 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::underflows 1496 97.02% 97.02% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::1000-5e+10 41 2.66% 99.68% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.74% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.06% 99.81% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.19% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::max_value 499963822636 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::total 1542 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateResidencyTicks::ON 496523303676 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2407350042824 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.numCycles 2904047101 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 55938514 # Number of instructions committed
|
|
system.cpu0.committedOps 67284601 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 59484081 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5858 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 4937125 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 7562453 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 59484081 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5858 # number of float instructions
|
|
system.cpu0.num_int_register_reads 108123008 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 41105221 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 4501 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1358 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 243174527 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 25739828 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 22504110 # number of memory refs
|
|
system.cpu0.num_load_insts 12361128 # Number of load instructions
|
|
system.cpu0.num_store_insts 10142982 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 2686495929.504804 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 217551171.495196 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.074913 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.925087 # Percentage of idle cycles
|
|
system.cpu0.Branches 12909756 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 46277611 67.22% 67.22% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 59345 0.09% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 4401 0.01% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.31% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 12361128 17.95% 85.27% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 10142982 14.73% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 68847670 # Class of executed instruction
|
|
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.tags.replacements 819197 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.827216 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 43241786 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 819709 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 52.752606 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.277381 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.549835 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607964 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391699 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 177132718 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 177132718 # Number of data accesses
|
|
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 11492240 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 11624339 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 23116579 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 9270030 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 9555793 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18825823 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200250 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192633 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 392883 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 225114 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 218358 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 443472 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 233001 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227267 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 20762270 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 21180132 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 41942402 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 20962520 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 21372765 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 42335285 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 199687 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 200107 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 399794 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 142706 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 155941 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 298647 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 56913 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61284 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 118197 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10855 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11725 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 342393 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 356048 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 698441 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 399306 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 417332 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 816638 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2969454500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2995849000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5965303500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5762218500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6859127500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 12621346000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 131663000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 147690500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 279353500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 166000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 8731673000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 9854976500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 18586649500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 8731673000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 9854976500 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 18586649500 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11691927 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11824446 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 23516373 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9412736 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9711734 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 19124470 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257163 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253917 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 511080 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 235969 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 230083 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 466052 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 233003 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227267 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 21104663 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 21536180 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 42640843 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 21361826 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 21790097 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 43151923 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017079 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016923 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.017001 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015161 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016057 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.015616 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221311 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.241354 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231269 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046002 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050960 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016224 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016533 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.016380 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018693 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019152 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.018925 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14870.544903 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.235389 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14920.943036 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40378.249688 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43985.401530 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42261.753843 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12129.249194 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12596.204691 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12371.722764 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 83000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25501.902784 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27678.786287 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 26611.624318 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21867.121957 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23614.236387 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 22759.961574 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.writebacks::writebacks 683616 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 683616 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 284 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 384 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 668 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7115 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 6934 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14049 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 284 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 384 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 284 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 384 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199403 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199723 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 399126 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142706 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155941 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 298647 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 56023 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60170 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 116193 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3740 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4791 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8531 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 342109 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 355664 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 697773 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 398132 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 415834 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 813966 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14422 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16716 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15099 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12490 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29521 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29206 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2764008500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2789776500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5553785000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5619512500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6703186500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12322699000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 725372500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 799789000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1525161500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48172500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 61674000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109846500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 164000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8383521000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9492963000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 17876484000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9108893500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10292752000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 19401645500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2833740000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3447478500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6281218500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2833740000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3447478500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6281218500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017055 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016891 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016972 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015161 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016057 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015616 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.217850 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.236967 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227348 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015850 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020823 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018305 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016210 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016515 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018638 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13861.418835 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13968.228496 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13914.866483 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39378.249688 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42985.401530 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41261.753843 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12947.762526 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13292.155559 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13126.104843 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12880.347594 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12872.886662 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12876.157543 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 82000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24505.409095 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26690.817738 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25619.340387 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22879.079049 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24752.069335 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23835.940936 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196487.311053 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206238.244795 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.963517 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95990.650723 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118040.077381 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.229673 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.tags.replacements 1698024 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 510.728400 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 113871338 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1698536 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 67.040874 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 25838751500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 417.467812 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 93.260588 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.815367 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.182150 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.997516 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 117268422 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 117268422 # Number of data accesses
|
|
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 56621226 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 57250112 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 113871338 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 56621226 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 57250112 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 113871338 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 56621226 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 57250112 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 113871338 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 854459 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 844083 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1698542 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 854459 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 844083 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1698542 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 854459 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 844083 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1698542 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11710586000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11696136000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 23406722000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 11710586000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 11696136000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 23406722000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 11710586000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 11696136000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 23406722000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57475685 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 58094195 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 115569880 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 57475685 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 58094195 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 115569880 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 57475685 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 58094195 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 115569880 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014866 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014530 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014866 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014530 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014866 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014530 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13705.263798 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13856.618366 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13780.478787 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13705.263798 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13856.618366 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13780.478787 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13705.263798 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13856.618366 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13780.478787 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.writebacks::writebacks 1698024 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 1698024 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 854459 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 844083 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 1698542 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 854459 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 844083 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 1698542 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 854459 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 844083 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 1698542 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10856127000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10852053000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 21708180000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10856127000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10852053000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 21708180000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10856127000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10852053000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 21708180000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014530 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014530 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014530 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12705.263798 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12856.618366 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12780.478787 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12705.263798 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12856.618366 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12780.478787 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12705.263798 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12856.618366 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12780.478787 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dtb.walker.walks 6542 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksShort 6542 # Table walker walks initiated with short descriptors
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1888 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4654 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 6542 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 6542 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 6542 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 5408 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 12327.385355 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 10604.258699 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 7039.389746 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::0-16383 4342 80.29% 80.29% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1062 19.64% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 5408 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples 1000192500 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 1000192500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total 1000192500 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 3546 65.57% 65.57% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::1M 1862 34.43% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 5408 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6542 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6542 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5408 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5408 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 11950 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 12325162 # DTB read hits
|
|
system.cpu1.dtb.read_misses 5607 # DTB read misses
|
|
system.cpu1.dtb.write_hits 9951712 # DTB write hits
|
|
system.cpu1.dtb.write_misses 935 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 3942 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 892 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 12330769 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 9952647 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 22276874 # DTB hits
|
|
system.cpu1.dtb.misses 6542 # DTB misses
|
|
system.cpu1.dtb.accesses 22283416 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.itb.walker.walks 3192 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksShort 3192 # Table walker walks initiated with short descriptors
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 694 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2498 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walkWaitTime::samples 3192 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 3192 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 3192 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 2373 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 12622.418879 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 10730.148321 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 7022.179008 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::0-8191 765 32.24% 32.24% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1087 45.81% 78.04% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::16384-24575 508 21.41% 99.45% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::24576-32767 12 0.51% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 2373 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 1679 70.75% 70.75% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::1M 694 29.25% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 2373 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3192 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3192 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2373 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2373 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 5565 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 58094195 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 3192 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 2321 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 58097387 # ITB inst accesses
|
|
system.cpu1.itb.hits 58094195 # DTB hits
|
|
system.cpu1.itb.misses 3192 # DTB misses
|
|
system.cpu1.itb.accesses 58097387 # DTB accesses
|
|
system.cpu1.numPwrStateTransitions 2962 # Number of power state transitions
|
|
system.cpu1.pwrStateClkGateDist::samples 1481 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::mean 1715351950.690074 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::stdev 49199578788.066856 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::underflows 1468 99.12% 99.12% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::1000-5e+10 10 0.68% 99.80% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::overflows 1 0.07% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::max_value 1799694213001 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::total 1481 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateResidencyTicks::ON 363437107528 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2540436238972 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.numCycles 2903699592 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 56533338 # Number of instructions committed
|
|
system.cpu1.committedOps 68322917 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 60427301 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 5303 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 4958033 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 7669947 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 60427301 # number of integer instructions
|
|
system.cpu1.num_fp_insts 5303 # number of float instructions
|
|
system.cpu1.num_int_register_reads 109945551 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 41554232 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 3948 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 246640123 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 26160975 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 22909081 # number of memory refs
|
|
system.cpu1.num_load_insts 12485523 # Number of load instructions
|
|
system.cpu1.num_store_insts 10423558 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 2692719592.304736 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 210979999.695264 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.072659 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.927341 # Percentage of idle cycles
|
|
system.cpu1.Branches 13011724 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 46912423 67.13% 67.13% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 55213 0.08% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.21% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 4054 0.01% 67.22% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.22% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.22% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.22% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 12485523 17.87% 85.08% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 10423558 14.92% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 69880905 # Class of executed instruction
|
|
system.iobus.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 46332000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 96000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 643000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 6280000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 36460500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 187670847 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.iocache.tags.replacements 36424 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.079286 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 309377087000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.079286 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.067455 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.067455 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328122 # Number of data accesses
|
|
system.iocache.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 36458 # number of overall misses
|
|
system.iocache.overall_misses::total 36458 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 29588377 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 29588377 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 4277963470 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4277963470 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 4307551847 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 4307551847 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 4307551847 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 4307551847 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 126446.055556 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126446.055556 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118097.489786 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 118097.489786 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 118151.073756 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 118151.073756 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 118151.073756 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 118151.073756 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17888377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 17888377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464657470 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2464657470 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 2482545847 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 2482545847 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 2482545847 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 2482545847 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76446.055556 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76446.055556 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68039.351535 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.351535 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68093.308657 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 68093.308657 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68093.308657 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 68093.308657 # average overall mshr miss latency
|
|
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.l2c.tags.replacements 88931 # number of replacements
|
|
system.l2c.tags.tagsinuse 64921.532624 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 4554640 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 154190 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 29.539140 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 50439.017527 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.855331 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000489 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4116.974919 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2621.771037 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.860553 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.964520 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 5479.024389 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 2258.063860 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.769638 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.062820 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.040005 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.083603 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.034455 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.990624 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65253 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6981 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 56097 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.995682 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 40592832 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 40592832 # Number of data accesses
|
|
system.l2c.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 6060 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3335 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 5248 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 2709 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 17352 # number of ReadReq hits
|
|
system.l2c.WritebackDirty_hits::writebacks 683616 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 683616 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 1666963 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 1666963 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 83335 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 82122 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 165457 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 846325 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 834210 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1680535 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 253515 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 258250 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 511765 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 6060 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 3335 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 846325 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 336850 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5248 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 2709 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 834210 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 340372 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2375109 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 6060 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 3335 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 846325 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 336850 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5248 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 2709 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 834210 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 340372 # number of overall hits
|
|
system.l2c.overall_hits::total 2375109 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 10 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1333 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1402 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2735 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 58027 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 72404 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 130431 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 8123 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 9860 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 17983 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 5651 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 6434 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 12085 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 8123 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 63678 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 9860 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 78838 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 160509 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 8123 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 63678 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 9860 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 78838 # number of overall misses
|
|
system.l2c.overall_misses::total 160509 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 251000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 84000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 433000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 851500 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 321500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 201500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 523000 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 161000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 4489796500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 5564391000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 10054187500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 658512500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 797268000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 1455780500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 478395500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 533868000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 1012263500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 251000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 658512500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 4968192000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 433000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 797268000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 6098259000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 12523083000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 658512500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 4968192000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.dtb.walker 433000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 797268000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 6098259000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 12523083000 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 6063 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 3336 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5253 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 2710 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 17362 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::writebacks 683616 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 683616 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 1666963 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 1666963 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1344 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1415 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2759 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 141362 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 154526 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 295888 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 854448 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 844070 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1698518 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 259166 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 264684 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 523850 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 6063 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 3336 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 854448 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 400528 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 5253 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 2710 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 844070 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 419210 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2535618 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 6063 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 3336 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 854448 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 400528 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 5253 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 2710 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 844070 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 419210 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2535618 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000300 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000369 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991815 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990813 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.991301 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.410485 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.468555 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.440812 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009507 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011681 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.010587 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021805 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.024308 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.023070 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000300 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.009507 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000369 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.011681 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.188063 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.063302 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000300 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.009507 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000369 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.011681 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.188063 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.063302 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average ReadReq miss latency
|
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system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86600 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 85150 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 241.185296 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 143.723252 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 191.224863 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 80500 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77374.265428 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76851.983316 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 77084.339613 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81067.647421 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80858.823529 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 80953.150197 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84656.786409 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82976.064657 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 83761.977658 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 81067.647421 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 78020.540846 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86600 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 80858.823529 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 77351.771988 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 78021.064239 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency
|
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system.l2c.overall_avg_miss_latency::cpu0.inst 81067.647421 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 78020.540846 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86600 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 80858.823529 # average overall miss latency
|
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system.l2c.overall_avg_miss_latency::cpu1.data 77351.771988 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 78021.064239 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 82443 # number of writebacks
|
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system.l2c.writebacks::total 82443 # number of writebacks
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system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses
|
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|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1333 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1402 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 58027 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 72404 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 130431 # number of ReadExReq MSHR misses
|
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system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8123 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9860 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 17983 # number of ReadCleanReq MSHR misses
|
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system.l2c.ReadSharedReq_mshr_misses::cpu0.data 5651 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6434 # number of ReadSharedReq MSHR misses
|
|
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|
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|
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|
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system.l2c.demand_mshr_misses::cpu0.inst 8123 # number of demand (read+write) MSHR misses
|
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|
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|
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system.l2c.demand_mshr_misses::cpu1.inst 9860 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::cpu1.data 78838 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::total 160509 # number of demand (read+write) MSHR misses
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|
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|
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system.l2c.overall_mshr_misses::cpu1.inst 9860 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.data 78838 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 160509 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
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system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14422 # number of ReadReq MSHR uncacheable
|
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system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16716 # number of ReadReq MSHR uncacheable
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system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
|
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|
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system.l2c.WriteReq_mshr_uncacheable::cpu1.data 12490 # number of WriteReq MSHR uncacheable
|
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|
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system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
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system.l2c.overall_mshr_uncacheable_misses::cpu0.data 29521 # number of overall MSHR uncacheable misses
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system.l2c.overall_mshr_uncacheable_misses::cpu1.data 29206 # number of overall MSHR uncacheable misses
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system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 221000 # number of ReadReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4840351000 # number of ReadExReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::total 8749877500 # number of ReadExReq MSHR miss cycles
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system.l2c.ReadCleanReq_mshr_miss_latency::total 1275950500 # number of ReadCleanReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421885500 # number of ReadSharedReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 469528000 # number of ReadSharedReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 221000 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::total 10917993000 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 577282500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 4331412000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 383000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 698668000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 5309879000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 10917993000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2653414500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3238477000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 6466403500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 574512000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2653414500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3238477000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 6466403500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000369 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991815 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990813 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.410485 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468555 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.440812 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009507 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011681 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010587 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.021805 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.024308 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023070 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009507 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.158985 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000369 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011681 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.188063 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.063302 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009507 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.158985 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000369 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011681 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.188063 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.063302 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 75150 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19038.259565 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19035.306705 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19036.745887 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67374.265428 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66851.983316 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67084.339613 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71067.647421 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70858.823529 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70953.150197 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74656.786409 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72976.064657 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73761.977658 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71067.647421 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68020.540846 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70858.823529 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67351.771988 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 68021.064239 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71067.647421 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68020.540846 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70858.823529 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67351.771988 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 68021.064239 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183983.809458 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193735.163915 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.023406 # average ReadReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89882.270248 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110883.962200 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.478915 # average overall mshr uncacheable latency
|
|
system.membus.snoop_filter.tot_requests 325065 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 134281 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 70472 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 118633 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 6722 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4501 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 128665 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 128665 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 30312 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438549 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 546141 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 619038 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15474044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 15637397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 17954517 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 498 # Total snoops (count)
|
|
system.membus.snoopTraffic 31744 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 267453 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.018325 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.134123 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 262552 98.17% 98.17% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 4901 1.83% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 267453 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 90447000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 831225280 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 950869500 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 1219123 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.snoop_filter.tot_requests 5058632 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2540376 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 38310 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.trans_dist::ReadReq 74735 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2297346 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 766059 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 1698024 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 142069 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 295888 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 295888 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1698542 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 524071 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 4401 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5113128 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581868 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17962 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 33975 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7746933 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217414776 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96411805 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 313896029 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 111009 # Total snoops (count)
|
|
system.toL2Bus.snoopTraffic 5360756 # Total snoop traffic (bytes)
|
|
system.toL2Bus.snoop_fanout::samples 2716918 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.021699 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.145698 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 2657964 97.83% 97.83% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 58954 2.17% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 2716918 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 4965727500 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 2556835000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1275921497 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 11916000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 22659000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|