8a9416ef8d
cpu/o3/alpha_dyn_inst.hh:
Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
Don't need to reset the state.
cpu/o3/commit_impl.hh:
Mark instructions as completed.
Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache.
--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
972 lines
26 KiB
C++
972 lines
26 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/o3/lsq_unit.hh"
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#include "base/str.hh"
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template <class Impl>
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LSQUnit<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
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Event *wb_event,
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LSQUnit<Impl> *lsq_ptr)
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: Event(&mainEventQueue),
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storeIdx(store_idx),
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wbEvent(wb_event),
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lsqPtr(lsq_ptr)
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{
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this->setFlags(Event::AutoDelete);
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}
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template <class Impl>
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void
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LSQUnit<Impl>::StoreCompletionEvent::process()
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{
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DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx);
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DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx);
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//lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
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if (lsqPtr->isSwitchedOut())
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return;
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lsqPtr->cpu->wakeCPU();
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if (wbEvent)
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wbEvent->process();
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lsqPtr->completeStore(storeIdx);
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}
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template <class Impl>
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const char *
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LSQUnit<Impl>::StoreCompletionEvent::description()
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{
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return "LSQ store completion event";
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}
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template <class Impl>
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LSQUnit<Impl>::LSQUnit()
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: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
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loadBlockedHandled(false)
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{
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}
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template<class Impl>
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void
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LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
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unsigned maxSQEntries, unsigned id)
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{
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DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
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switchedOut = false;
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lsqID = id;
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LQEntries = maxLQEntries;
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SQEntries = maxSQEntries;
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loadQueue.resize(LQEntries);
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storeQueue.resize(SQEntries);
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// May want to initialize these entries to NULL
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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cachePorts = params->cachePorts;
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dcacheInterface = params->dcacheInterface;
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loadFaultInst = storeFaultInst = memDepViolator = NULL;
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blockedLoadSeqNum = 0;
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}
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template<class Impl>
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std::string
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LSQUnit<Impl>::name() const
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{
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if (Impl::MaxThreads == 1) {
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return iewStage->name() + ".lsq";
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} else {
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return iewStage->name() + ".lsq.thread." + to_string(lsqID);
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearLQ()
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{
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loadQueue.clear();
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearSQ()
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{
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storeQueue.clear();
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}
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#if 0
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template<class Impl>
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void
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LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
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{
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DPRINTF(LSQUnit, "Setting the page table pointer.\n");
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pTable = pt_ptr;
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}
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#endif
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template<class Impl>
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void
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LSQUnit<Impl>::switchOut()
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{
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switchedOut = true;
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for (int i = 0; i < loadQueue.size(); ++i)
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loadQueue[i] = NULL;
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while (storesToWB > 0 &&
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storeWBIdx != storeTail &&
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storeQueue[storeWBIdx].inst &&
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storeQueue[storeWBIdx].canWB) {
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if (storeQueue[storeWBIdx].size == 0 ||
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storeQueue[storeWBIdx].inst->isDataPrefetch() ||
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storeQueue[storeWBIdx].committed ||
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storeQueue[storeWBIdx].req->flags & LOCKED) {
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incrStIdx(storeWBIdx);
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continue;
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}
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assert(storeQueue[storeWBIdx].req);
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assert(!storeQueue[storeWBIdx].committed);
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MemReqPtr req = storeQueue[storeWBIdx].req;
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storeQueue[storeWBIdx].committed = true;
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req->cmd = Write;
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req->completionEvent = NULL;
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req->time = curTick;
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assert(!req->data);
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req->data = new uint8_t[64];
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memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
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DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
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"to Addr:%#x, data:%#x [sn:%lli]\n",
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storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
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req->paddr, *(req->data),
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storeQueue[storeWBIdx].inst->seqNum);
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switch(storeQueue[storeWBIdx].size) {
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case 1:
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cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
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break;
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case 2:
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cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
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break;
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case 4:
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cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
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break;
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case 8:
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cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
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break;
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default:
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panic("Unexpected store size!\n");
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}
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incrStIdx(storeWBIdx);
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::takeOverFrom()
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{
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switchedOut = false;
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loads = stores = storesToWB = 0;
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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loadFaultInst = storeFaultInst = memDepViolator = NULL;
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blockedLoadSeqNum = 0;
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stalled = false;
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isLoadBlocked = false;
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loadBlockedHandled = false;
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}
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template<class Impl>
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void
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LSQUnit<Impl>::resizeLQ(unsigned size)
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{
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assert( size >= LQEntries);
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if (size > LQEntries) {
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while (size > loadQueue.size()) {
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DynInstPtr dummy;
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loadQueue.push_back(dummy);
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LQEntries++;
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}
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} else {
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LQEntries = size;
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::resizeSQ(unsigned size)
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{
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if (size > SQEntries) {
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while (size > storeQueue.size()) {
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SQEntry dummy;
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storeQueue.push_back(dummy);
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SQEntries++;
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}
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} else {
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SQEntries = size;
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}
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insert(DynInstPtr &inst)
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{
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// Make sure we really have a memory reference.
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assert(inst->isMemRef());
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// Make sure it's one of the two classes of memory references.
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assert(inst->isLoad() || inst->isStore());
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if (inst->isLoad()) {
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insertLoad(inst);
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} else {
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insertStore(inst);
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}
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inst->setInLSQ();
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
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{
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assert((loadTail + 1) % LQEntries != loadHead && loads < LQEntries);
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DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
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load_inst->readPC(), loadTail, load_inst->seqNum);
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load_inst->lqIdx = loadTail;
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if (stores == 0) {
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load_inst->sqIdx = -1;
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} else {
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load_inst->sqIdx = storeTail;
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}
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loadQueue[loadTail] = load_inst;
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incrLdIdx(loadTail);
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++loads;
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
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{
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// Make sure it is not full before inserting an instruction.
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assert((storeTail + 1) % SQEntries != storeHead);
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assert(stores < SQEntries);
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DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
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store_inst->readPC(), storeTail, store_inst->seqNum);
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store_inst->sqIdx = storeTail;
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store_inst->lqIdx = loadTail;
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storeQueue[storeTail] = SQEntry(store_inst);
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incrStIdx(storeTail);
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++stores;
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}
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template <class Impl>
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typename Impl::DynInstPtr
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LSQUnit<Impl>::getMemDepViolator()
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{
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DynInstPtr temp = memDepViolator;
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memDepViolator = NULL;
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return temp;
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}
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template <class Impl>
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unsigned
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LSQUnit<Impl>::numFreeEntries()
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{
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unsigned free_lq_entries = LQEntries - loads;
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unsigned free_sq_entries = SQEntries - stores;
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|
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
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// empty/full conditions. Subtract 1 from the free entries.
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if (free_lq_entries < free_sq_entries) {
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return free_lq_entries - 1;
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} else {
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return free_sq_entries - 1;
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}
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}
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|
template <class Impl>
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int
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LSQUnit<Impl>::numLoadsReady()
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{
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int load_idx = loadHead;
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int retval = 0;
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|
|
while (load_idx != loadTail) {
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assert(loadQueue[load_idx]);
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|
|
if (loadQueue[load_idx]->readyToIssue()) {
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++retval;
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}
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}
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|
|
return retval;
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}
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|
|
#if 0
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template <class Impl>
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Fault
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LSQUnit<Impl>::executeLoad()
|
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{
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Fault load_fault = NoFault;
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DynInstPtr load_inst;
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|
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assert(readyLoads.size() != 0);
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|
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// Execute a ready load.
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LdMapIt ready_it = readyLoads.begin();
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load_inst = (*ready_it).second;
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|
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// Execute the instruction, which is held in the data portion of the
|
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// iterator.
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load_fault = load_inst->execute();
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|
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// If it executed successfully, then switch it over to the executed
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// loads list.
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if (load_fault == NoFault) {
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executedLoads[load_inst->seqNum] = load_inst;
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readyLoads.erase(ready_it);
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} else {
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loadFaultInst = load_inst;
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}
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|
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return load_fault;
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}
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#endif
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|
|
template <class Impl>
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Fault
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LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
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{
|
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// Execute a specific load.
|
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Fault load_fault = NoFault;
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DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
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inst->readPC(),inst->seqNum);
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|
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// Make sure it's really in the list.
|
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// Normally it should always be in the list. However,
|
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/* due to a syscall it may not be the list.
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#ifdef DEBUG
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int i = loadHead;
|
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while (1) {
|
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if (i == loadTail && !find(inst)) {
|
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assert(0 && "Load not in the queue!");
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} else if (loadQueue[i] == inst) {
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break;
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}
|
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|
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i = i + 1;
|
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if (i >= LQEntries) {
|
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i = 0;
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}
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}
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#endif // DEBUG*/
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|
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// load_fault = inst->initiateAcc();
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load_fault = inst->execute();
|
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|
|
// If the instruction faulted, then we need to send it along to commit
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// without the instruction completing.
|
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if (load_fault != NoFault) {
|
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// Maybe just set it as can commit here, although that might cause
|
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// some other problems with sending traps to the ROB too quickly.
|
|
iewStage->instToCommit(inst);
|
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iewStage->activityThisCycle();
|
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}
|
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|
|
return load_fault;
|
|
}
|
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|
|
template <class Impl>
|
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Fault
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|
LSQUnit<Impl>::executeLoad(int lq_idx)
|
|
{
|
|
// Very hackish. Not sure the best way to check that this
|
|
// instruction is at the head of the ROB. I should have some sort
|
|
// of extra information here so that I'm not overloading the
|
|
// canCommit signal for 15 different things.
|
|
loadQueue[lq_idx]->setCanCommit();
|
|
Fault ret_fault = executeLoad(loadQueue[lq_idx]);
|
|
loadQueue[lq_idx]->clearCanCommit();
|
|
return ret_fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|
{
|
|
using namespace TheISA;
|
|
// Make sure that a store exists.
|
|
assert(stores != 0);
|
|
|
|
int store_idx = store_inst->sqIdx;
|
|
|
|
DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
|
|
store_inst->readPC(), store_inst->seqNum);
|
|
|
|
// Check the recently completed loads to see if any match this store's
|
|
// address. If so, then we have a memory ordering violation.
|
|
int load_idx = store_inst->lqIdx;
|
|
|
|
Fault store_fault = store_inst->initiateAcc();
|
|
// Fault store_fault = store_inst->execute();
|
|
|
|
// Store size should now be available. Use it to get proper offset for
|
|
// addr comparisons.
|
|
int size = storeQueue[store_idx].size;
|
|
|
|
if (size == 0) {
|
|
DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
|
|
store_inst->readPC(),store_inst->seqNum);
|
|
|
|
return store_fault;
|
|
}
|
|
|
|
assert(store_fault == NoFault);
|
|
|
|
if (!storeFaultInst) {
|
|
if (store_fault != NoFault) {
|
|
panic("Fault in a store instruction!");
|
|
storeFaultInst = store_inst;
|
|
} else if (store_inst->isNonSpeculative()) {
|
|
// Nonspeculative accesses (namely store conditionals)
|
|
// need to set themselves as able to writeback if we
|
|
// haven't had a fault by here.
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
++storesToWB;
|
|
}
|
|
}
|
|
|
|
if (!memDepViolator) {
|
|
while (load_idx != loadTail) {
|
|
// Actually should only check loads that have actually executed
|
|
// Might be safe because effAddr is set to InvalAddr when the
|
|
// dyn inst is created.
|
|
|
|
// Must actually check all addrs in the proper size range
|
|
// Which is more correct than needs to be. What if for now we just
|
|
// assume all loads are quad-word loads, and do the addr based
|
|
// on that.
|
|
// @todo: Fix this, magic number being used here
|
|
if ((loadQueue[load_idx]->effAddr >> 8) ==
|
|
(store_inst->effAddr >> 8)) {
|
|
// A load incorrectly passed this store. Squash and refetch.
|
|
// For now return a fault to show that it was unsuccessful.
|
|
memDepViolator = loadQueue[load_idx];
|
|
|
|
return genMachineCheckFault();
|
|
}
|
|
|
|
incrLdIdx(load_idx);
|
|
}
|
|
|
|
// If we've reached this point, there was no violation.
|
|
memDepViolator = NULL;
|
|
}
|
|
|
|
return store_fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoad()
|
|
{
|
|
assert(loadQueue[loadHead]);
|
|
|
|
DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
|
|
loadQueue[loadHead]->readPC());
|
|
|
|
|
|
loadQueue[loadHead] = NULL;
|
|
|
|
incrLdIdx(loadHead);
|
|
|
|
--loads;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoad(InstSeqNum &inst)
|
|
{
|
|
// Hopefully I don't use this function too much
|
|
panic("Don't use this function!");
|
|
|
|
int i = loadHead;
|
|
while (1) {
|
|
if (i == loadTail) {
|
|
assert(0 && "Load not in the queue!");
|
|
} else if (loadQueue[i]->seqNum == inst) {
|
|
break;
|
|
}
|
|
|
|
++i;
|
|
if (i >= LQEntries) {
|
|
i = 0;
|
|
}
|
|
}
|
|
|
|
loadQueue[i]->removeInLSQ();
|
|
loadQueue[i] = NULL;
|
|
--loads;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
|
{
|
|
assert(loads == 0 || loadQueue[loadHead]);
|
|
|
|
while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
|
|
commitLoad();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
|
|
{
|
|
assert(stores == 0 || storeQueue[storeHead].inst);
|
|
|
|
int store_idx = storeHead;
|
|
|
|
while (store_idx != storeTail) {
|
|
assert(storeQueue[store_idx].inst);
|
|
if (!storeQueue[store_idx].canWB) {
|
|
if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
|
|
break;
|
|
}
|
|
DPRINTF(LSQUnit, "Marking store as able to write back, PC "
|
|
"%#x [sn:%lli]\n",
|
|
storeQueue[store_idx].inst->readPC(),
|
|
storeQueue[store_idx].inst->seqNum);
|
|
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
// --stores;
|
|
++storesToWB;
|
|
}
|
|
|
|
incrStIdx(store_idx);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::writebackStores()
|
|
{
|
|
while (storesToWB > 0 &&
|
|
storeWBIdx != storeTail &&
|
|
storeQueue[storeWBIdx].inst &&
|
|
storeQueue[storeWBIdx].canWB &&
|
|
usedPorts < cachePorts) {
|
|
|
|
if (storeQueue[storeWBIdx].size == 0) {
|
|
completeStore(storeWBIdx);
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
|
}
|
|
|
|
if (dcacheInterface && dcacheInterface->isBlocked()) {
|
|
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
|
|
" is blocked!\n");
|
|
break;
|
|
}
|
|
|
|
++usedPorts;
|
|
|
|
if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
|
}
|
|
|
|
assert(storeQueue[storeWBIdx].req);
|
|
assert(!storeQueue[storeWBIdx].committed);
|
|
|
|
MemReqPtr req = storeQueue[storeWBIdx].req;
|
|
storeQueue[storeWBIdx].committed = true;
|
|
|
|
// Fault fault = cpu->translateDataWriteReq(req);
|
|
req->cmd = Write;
|
|
req->completionEvent = NULL;
|
|
req->time = curTick;
|
|
assert(!req->data);
|
|
req->data = new uint8_t[64];
|
|
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
|
|
|
|
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
|
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
|
storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
|
|
req->paddr, *(req->data),
|
|
storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
switch(storeQueue[storeWBIdx].size) {
|
|
case 1:
|
|
cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
case 2:
|
|
cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
case 4:
|
|
cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
case 8:
|
|
cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
|
|
break;
|
|
default:
|
|
panic("Unexpected store size!\n");
|
|
}
|
|
if (!(req->flags & LOCKED)) {
|
|
storeQueue[storeWBIdx].inst->setCompleted();
|
|
}
|
|
|
|
if (dcacheInterface) {
|
|
assert(!req->completionEvent);
|
|
StoreCompletionEvent *store_event = new
|
|
StoreCompletionEvent(storeWBIdx, NULL, this);
|
|
req->completionEvent = store_event;
|
|
|
|
MemAccessResult result = dcacheInterface->access(req);
|
|
|
|
if (isStalled() &&
|
|
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
"load idx:%i\n",
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
}
|
|
|
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
|
typename IEW::LdWritebackEvent *wb = NULL;
|
|
if (req->flags & LOCKED) {
|
|
// Stx_C should not generate a system port transaction,
|
|
// but that might be hard to accomplish.
|
|
wb = new typename
|
|
IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
|
|
iewStage);
|
|
store_event->wbEvent = wb;
|
|
}
|
|
|
|
DPRINTF(LSQUnit,"D-Cache Write Miss!\n");
|
|
|
|
DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
|
|
storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
lastDcacheStall = curTick;
|
|
|
|
// _status = DcacheMissStall;
|
|
|
|
//mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
//DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
|
|
|
|
// Increment stat here or something
|
|
} else {
|
|
DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
|
|
storeWBIdx);
|
|
|
|
DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
|
|
storeQueue[storeWBIdx].inst->seqNum);
|
|
|
|
|
|
if (req->flags & LOCKED) {
|
|
// Stx_C does not generate a system port transaction.
|
|
/*
|
|
if (req->flags & UNCACHEABLE) {
|
|
req->result = 2;
|
|
} else {
|
|
if (cpu->lockFlag && cpu->lockAddr == req->paddr) {
|
|
req->result=1;
|
|
} else {
|
|
req->result = 0;
|
|
}
|
|
}
|
|
*/
|
|
typename IEW::LdWritebackEvent *wb =
|
|
new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
|
|
iewStage);
|
|
store_event->wbEvent = wb;
|
|
}
|
|
}
|
|
|
|
incrStIdx(storeWBIdx);
|
|
} else {
|
|
panic("Must HAVE DCACHE!!!!!\n");
|
|
}
|
|
}
|
|
|
|
// Not sure this should set it to 0.
|
|
usedPorts = 0;
|
|
|
|
assert(stores >= 0 && storesToWB >= 0);
|
|
}
|
|
|
|
/*template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
|
|
{
|
|
list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
|
|
mshrSeqNums.end(),
|
|
seqNum);
|
|
|
|
if (mshr_it != mshrSeqNums.end()) {
|
|
mshrSeqNums.erase(mshr_it);
|
|
DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
|
|
}
|
|
}*/
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
|
{
|
|
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
|
|
"(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
|
|
|
|
int load_idx = loadTail;
|
|
decrLdIdx(load_idx);
|
|
|
|
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
|
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
|
|
"[sn:%lli]\n",
|
|
loadQueue[load_idx]->readPC(),
|
|
loadQueue[load_idx]->seqNum);
|
|
|
|
if (isStalled() && load_idx == stallingLoadIdx) {
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
stallingLoadIdx = 0;
|
|
}
|
|
|
|
loadQueue[load_idx]->squashed = true;
|
|
loadQueue[load_idx] = NULL;
|
|
--loads;
|
|
|
|
// Inefficient!
|
|
loadTail = load_idx;
|
|
|
|
decrLdIdx(load_idx);
|
|
}
|
|
|
|
if (isLoadBlocked) {
|
|
if (squashed_num < blockedLoadSeqNum) {
|
|
isLoadBlocked = false;
|
|
loadBlockedHandled = false;
|
|
blockedLoadSeqNum = 0;
|
|
}
|
|
}
|
|
|
|
int store_idx = storeTail;
|
|
decrStIdx(store_idx);
|
|
|
|
while (stores != 0 &&
|
|
storeQueue[store_idx].inst->seqNum > squashed_num) {
|
|
|
|
if (storeQueue[store_idx].canWB) {
|
|
break;
|
|
}
|
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
|
|
"idx:%i [sn:%lli]\n",
|
|
storeQueue[store_idx].inst->readPC(),
|
|
store_idx, storeQueue[store_idx].inst->seqNum);
|
|
|
|
// I don't think this can happen. It should have been cleared by the
|
|
// stalling load.
|
|
if (isStalled() &&
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
panic("Is stalled should have been cleared by stalling load!\n");
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
}
|
|
|
|
storeQueue[store_idx].inst->squashed = true;
|
|
storeQueue[store_idx].inst = NULL;
|
|
storeQueue[store_idx].canWB = 0;
|
|
|
|
if (storeQueue[store_idx].req) {
|
|
assert(!storeQueue[store_idx].req->completionEvent);
|
|
}
|
|
storeQueue[store_idx].req = NULL;
|
|
--stores;
|
|
|
|
// Inefficient!
|
|
storeTail = store_idx;
|
|
|
|
decrStIdx(store_idx);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::dumpInsts()
|
|
{
|
|
cprintf("Load store queue: Dumping instructions.\n");
|
|
cprintf("Load queue size: %i\n", loads);
|
|
cprintf("Load queue: ");
|
|
|
|
int load_idx = loadHead;
|
|
|
|
while (load_idx != loadTail && loadQueue[load_idx]) {
|
|
cprintf("%#x ", loadQueue[load_idx]->readPC());
|
|
|
|
incrLdIdx(load_idx);
|
|
}
|
|
|
|
cprintf("Store queue size: %i\n", stores);
|
|
cprintf("Store queue: ");
|
|
|
|
int store_idx = storeHead;
|
|
|
|
while (store_idx != storeTail && storeQueue[store_idx].inst) {
|
|
cprintf("%#x ", storeQueue[store_idx].inst->readPC());
|
|
|
|
incrStIdx(store_idx);
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::completeStore(int store_idx)
|
|
{
|
|
assert(storeQueue[store_idx].inst);
|
|
storeQueue[store_idx].completed = true;
|
|
--storesToWB;
|
|
// A bit conservative because a store completion may not free up entries,
|
|
// but hopefully avoids two store completions in one cycle from making
|
|
// the CPU tick twice.
|
|
cpu->activityThisCycle();
|
|
|
|
if (store_idx == storeHead) {
|
|
do {
|
|
incrStIdx(storeHead);
|
|
|
|
--stores;
|
|
} while (storeQueue[storeHead].completed &&
|
|
storeHead != storeTail);
|
|
|
|
iewStage->updateLSQNextCycle = true;
|
|
}
|
|
|
|
DPRINTF(LSQUnit, "Store head idx:%i\n", storeHead);
|
|
|
|
if (isStalled() &&
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
"load idx:%i\n",
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::incrStIdx(int &store_idx)
|
|
{
|
|
if (++store_idx >= SQEntries)
|
|
store_idx = 0;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::decrStIdx(int &store_idx)
|
|
{
|
|
if (--store_idx < 0)
|
|
store_idx += SQEntries;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::incrLdIdx(int &load_idx)
|
|
{
|
|
if (++load_idx >= LQEntries)
|
|
load_idx = 0;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::decrLdIdx(int &load_idx)
|
|
{
|
|
if (--load_idx < 0)
|
|
load_idx += LQEntries;
|
|
}
|