5b557a314f
This gets rid of cryptic bits of code with lots of bit manipulation, and makes some comments redundant.
163 lines
4.6 KiB
C++
163 lines
4.6 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#ifndef __ARCH_SPARC_MISCREGS_HH__
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#define __ARCH_SPARC_MISCREGS_HH__
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#include "base/bitunion.hh"
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#include "base/types.hh"
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namespace SparcISA
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{
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enum MiscRegIndex
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{
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/** Ancillary State Registers */
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// MISCREG_Y,
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// MISCREG_CCR,
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MISCREG_ASI,
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MISCREG_TICK,
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MISCREG_FPRS,
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MISCREG_PCR,
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MISCREG_PIC,
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MISCREG_GSR,
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MISCREG_SOFTINT_SET,
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MISCREG_SOFTINT_CLR,
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MISCREG_SOFTINT, /* 10 */
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MISCREG_TICK_CMPR,
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MISCREG_STICK,
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MISCREG_STICK_CMPR,
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/** Privilged Registers */
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MISCREG_TPC,
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MISCREG_TNPC,
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MISCREG_TSTATE,
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MISCREG_TT,
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MISCREG_PRIVTICK,
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MISCREG_TBA,
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MISCREG_PSTATE, /* 20 */
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MISCREG_TL,
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MISCREG_PIL,
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MISCREG_CWP,
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// MISCREG_CANSAVE,
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// MISCREG_CANRESTORE,
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// MISCREG_CLEANWIN,
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// MISCREG_OTHERWIN,
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// MISCREG_WSTATE,
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MISCREG_GL,
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/** Hyper privileged registers */
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MISCREG_HPSTATE, /* 30 */
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MISCREG_HTSTATE,
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MISCREG_HINTP,
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MISCREG_HTBA,
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MISCREG_HVER,
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MISCREG_STRAND_STS_REG,
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MISCREG_HSTICK_CMPR,
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/** Floating Point Status Register */
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MISCREG_FSR,
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/** MMU Internal Registers */
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MISCREG_MMU_P_CONTEXT,
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MISCREG_MMU_S_CONTEXT, /* 40 */
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MISCREG_MMU_PART_ID,
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MISCREG_MMU_LSU_CTRL,
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/** Scratchpad regiscers **/
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MISCREG_SCRATCHPAD_R0, /* 60 */
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MISCREG_SCRATCHPAD_R1,
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MISCREG_SCRATCHPAD_R2,
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MISCREG_SCRATCHPAD_R3,
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MISCREG_SCRATCHPAD_R4,
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MISCREG_SCRATCHPAD_R5,
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MISCREG_SCRATCHPAD_R6,
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MISCREG_SCRATCHPAD_R7,
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/* CPU Queue Registers */
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MISCREG_QUEUE_CPU_MONDO_HEAD,
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MISCREG_QUEUE_CPU_MONDO_TAIL,
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MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
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MISCREG_QUEUE_DEV_MONDO_TAIL,
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MISCREG_QUEUE_RES_ERROR_HEAD,
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MISCREG_QUEUE_RES_ERROR_TAIL,
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MISCREG_QUEUE_NRES_ERROR_HEAD,
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MISCREG_QUEUE_NRES_ERROR_TAIL,
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/* All the data for the TLB packed up in one register. */
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MISCREG_TLB_DATA,
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MISCREG_NUMMISCREGS
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};
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BitUnion64(HPSTATE)
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Bitfield<0> tlz;
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Bitfield<2> hpriv;
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Bitfield<5> red;
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Bitfield<10> ibe;
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Bitfield<11> id; // this impl. dependent (id) field m
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EndBitUnion(HPSTATE)
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BitUnion16(PSTATE)
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Bitfield<1> ie;
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Bitfield<2> priv;
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Bitfield<3> am;
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Bitfield<4> pef;
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Bitfield<6, 7> mm;
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Bitfield<8> tle;
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Bitfield<9> cle;
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Bitfield<10> pid0;
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Bitfield<11> pid1;
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EndBitUnion(PSTATE)
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struct STS
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{
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const static int st_idle = 0x00;
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const static int st_wait = 0x01;
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const static int st_halt = 0x02;
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const static int st_run = 0x05;
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const static int st_spec_run = 0x07;
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const static int st_spec_rdy = 0x13;
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const static int st_ready = 0x19;
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const static int active = 0x01;
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const static int speculative = 0x04;
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const static int shft_id = 8;
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const static int shft_fsm0 = 31;
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const static int shft_fsm1 = 26;
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const static int shft_fsm2 = 21;
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const static int shft_fsm3 = 16;
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};
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const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
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const int NumMiscRegs = MISCREG_NUMMISCREGS;
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}
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#endif
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