Chander Sudanthi 8a2ca2fd24 ARM: Fix MPIDR and MIDR register implementation. ... This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register.		2012-06-05 01:23:10 -04:00
..
alpha	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
arm	ARM: Fix MPIDR and MIDR register implementation.	2012-06-05 01:23:10 -04:00
generic	ISA,CPU: Generalize and split out the components of the decode cache.	2012-05-26 13:45:12 -07:00
mips	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
noisa	cpu: add separate stats for insts/ops both globally and per cpu model	2012-02-12 16:07:39 -06:00
power	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
sparc	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
x86	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
isa_parser.py	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	CPU: Merge the predecoder and decoder.	2012-05-26 13:44:46 -07:00