Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
54 lines
4.8 KiB
Text
54 lines
4.8 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 24803 # Simulator instruction rate (inst/s)
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host_mem_usage 193824 # Number of bytes of host memory used
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host_seconds 0.23 # Real time elapsed on the host
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host_tick_rate 12384497 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5656 # Number of instructions simulated
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sim_seconds 0.000003 # Number of seconds simulated
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sim_ticks 2828000 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 5657 # number of cpu cycles simulated
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system.cpu.num_insts 5656 # Number of instructions executed
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system.cpu.num_refs 2055 # Number of memory references
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system.cpu.tlb.accesses 0 # DTB accesses
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system.cpu.tlb.accesses 0 # DTB accesses
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system.cpu.tlb.hits 0 # DTB hits
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system.cpu.tlb.hits 0 # DTB hits
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system.cpu.tlb.misses 0 # DTB misses
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system.cpu.tlb.misses 0 # DTB misses
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system.cpu.tlb.read_accesses 0 # DTB read accesses
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system.cpu.tlb.read_accesses 0 # DTB read accesses
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system.cpu.tlb.read_hits 0 # DTB read hits
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system.cpu.tlb.read_hits 0 # DTB read hits
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system.cpu.tlb.read_misses 0 # DTB read misses
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system.cpu.tlb.read_misses 0 # DTB read misses
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system.cpu.tlb.write_accesses 0 # DTB write accesses
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system.cpu.tlb.write_accesses 0 # DTB write accesses
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system.cpu.tlb.write_hits 0 # DTB write hits
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system.cpu.tlb.write_hits 0 # DTB write hits
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system.cpu.tlb.write_misses 0 # DTB write misses
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system.cpu.tlb.write_misses 0 # DTB write misses
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system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
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---------- End Simulation Statistics ----------
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