9b05e96b9e
Change RAS to fix issues with predicated call/return instructions. Handled all cases in the life of a predicated call and return instruction.
518 lines
18 KiB
C++
518 lines
18 KiB
C++
/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include <algorithm>
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#include "arch/isa_traits.hh"
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#include "arch/types.hh"
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#include "arch/utility.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/o3/bpred_unit.hh"
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#include "debug/Fetch.hh"
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#include "params/DerivO3CPU.hh"
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template<class Impl>
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BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params)
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: _name(params->name + ".BPredUnit"),
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BTB(params->BTBEntries,
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params->BTBTagSize,
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params->instShiftAmt)
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{
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// Setup the selected predictor.
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if (params->predType == "local") {
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localBP = new LocalBP(params->localPredictorSize,
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params->localCtrBits,
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params->instShiftAmt);
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predictor = Local;
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} else if (params->predType == "tournament") {
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tournamentBP = new TournamentBP(params->localPredictorSize,
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params->localCtrBits,
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params->localHistoryTableSize,
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params->localHistoryBits,
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params->globalPredictorSize,
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params->globalHistoryBits,
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params->globalCtrBits,
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params->choicePredictorSize,
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params->choiceCtrBits,
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params->instShiftAmt);
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predictor = Tournament;
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} else {
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fatal("Invalid BP selected!");
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}
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for (int i=0; i < Impl::MaxThreads; i++)
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RAS[i].init(params->RASSize);
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}
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template <class Impl>
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void
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BPredUnit<Impl>::regStats()
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{
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lookups
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.name(name() + ".lookups")
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.desc("Number of BP lookups")
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;
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condPredicted
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.name(name() + ".condPredicted")
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.desc("Number of conditional branches predicted")
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;
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condIncorrect
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.name(name() + ".condIncorrect")
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.desc("Number of conditional branches incorrect")
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;
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BTBLookups
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.name(name() + ".BTBLookups")
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.desc("Number of BTB lookups")
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;
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BTBHits
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.name(name() + ".BTBHits")
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.desc("Number of BTB hits")
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;
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BTBCorrect
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.name(name() + ".BTBCorrect")
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.desc("Number of correct BTB predictions (this stat may not "
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"work properly.")
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;
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usedRAS
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.name(name() + ".usedRAS")
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.desc("Number of times the RAS was used to get a target.")
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;
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RASIncorrect
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.name(name() + ".RASInCorrect")
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.desc("Number of incorrect RAS predictions.")
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;
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}
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template <class Impl>
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void
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BPredUnit<Impl>::switchOut()
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{
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// Clear any state upon switch out.
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for (int i = 0; i < Impl::MaxThreads; ++i) {
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squash(0, i);
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::takeOverFrom()
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{
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// Can reset all predictor state, but it's not necessarily better
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// than leaving it be.
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/*
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for (int i = 0; i < Impl::MaxThreads; ++i)
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RAS[i].reset();
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BP.reset();
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BTB.reset();
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*/
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}
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template <class Impl>
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bool
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BPredUnit<Impl>::predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid)
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{
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// See if branch predictor predicts taken.
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// If so, get its target addr either from the BTB or the RAS.
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// Save off record of branch stuff so the RAS can be fixed
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// up once it's done.
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bool pred_taken = false;
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TheISA::PCState target = pc;
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++lookups;
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void *bp_history = NULL;
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if (inst->isUncondCtrl()) {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Unconditional control.\n", tid);
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pred_taken = true;
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// Tell the BP there was an unconditional branch.
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BPUncond(bp_history);
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} else {
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++condPredicted;
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pred_taken = BPLookup(pc.instAddr(), bp_history);
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DPRINTF(Fetch, "BranchPred:[tid:%i]: [sn:%i] Branch predictor"
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" predicted %i for PC %s\n",
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tid, inst->seqNum, pred_taken, inst->pcState());
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}
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DPRINTF(Fetch, "BranchPred: [tid:%i]: [sn:%i] Creating prediction history "
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"for PC %s\n",
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tid, inst->seqNum, inst->pcState());
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PredictorHistory predict_record(inst->seqNum, pc.instAddr(),
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pred_taken, bp_history, tid);
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// Now lookup in the BTB or RAS.
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if (pred_taken) {
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if (inst->isReturn()) {
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++usedRAS;
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predict_record.wasReturn = true;
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// If it's a function return call, then look up the address
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// in the RAS.
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TheISA::PCState rasTop = RAS[tid].top();
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target = TheISA::buildRetPC(pc, rasTop);
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// Record the top entry of the RAS, and its index.
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predict_record.usedRAS = true;
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predict_record.RASIndex = RAS[tid].topIdx();
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predict_record.RASTarget = rasTop;
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assert(predict_record.RASIndex < 16);
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RAS[tid].pop();
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s is a return, "
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"RAS predicted target: %s, RAS index: %i.\n",
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tid, inst->pcState(), target, predict_record.RASIndex);
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} else {
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++BTBLookups;
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if (inst->isCall()) {
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RAS[tid].push(pc);
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// Record that it was a call so that the top RAS entry can
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// be popped off if the speculation is incorrect.
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predict_record.wasCall = true;
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s was a "
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"call, adding %s to the RAS index: %i.\n",
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tid, inst->pcState(), pc, RAS[tid].topIdx());
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}
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if (BTB.valid(pc.instAddr(), tid)) {
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++BTBHits;
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predict_record.validBTB = true;
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// If it's not a return, use the BTB to get the target addr.
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target = BTB.lookup(pc.instAddr(), tid);
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s predicted"
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" target is %s.\n", tid, inst->pcState(), target);
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} else {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: BTB doesn't have a "
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"valid entry.\n",tid);
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pred_taken = false;
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// The Direction of the branch predictor is altered because the
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// BTB did not have an entry
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// The predictor needs to be updated accordingly
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if (!inst->isCall() && !inst->isReturn()) {
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BPBTBUpdate(pc.instAddr(), bp_history);
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DPRINTF(Fetch, "BranchPred: [tid:%i]:[sn:%i] BPBTBUpdate"
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" called for %s\n",
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tid, inst->seqNum, inst->pcState());
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} else if (inst->isCall() && !inst->isUncondCtrl()) {
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RAS[tid].pop();
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}
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TheISA::advancePC(target, inst->staticInst);
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}
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}
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} else {
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if (inst->isReturn()) {
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predict_record.wasReturn = true;
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}
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TheISA::advancePC(target, inst->staticInst);
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}
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pc = target;
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predHist[tid].push_front(predict_record);
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DPRINTF(Fetch, "BranchPred: [tid:%i]: [sn:%i]: History entry added."
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"predHist.size(): %i\n", tid, inst->seqNum, predHist[tid].size());
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return pred_taken;
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}
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template <class Impl>
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void
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BPredUnit<Impl>::update(const InstSeqNum &done_sn, ThreadID tid)
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{
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Committing branches until "
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"[sn:%lli].\n", tid, done_sn);
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while (!predHist[tid].empty() &&
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predHist[tid].back().seqNum <= done_sn) {
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// Update the branch predictor with the correct results.
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BPUpdate(predHist[tid].back().pc,
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predHist[tid].back().predTaken,
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predHist[tid].back().bpHistory, false);
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predHist[tid].pop_back();
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, ThreadID tid)
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{
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History &pred_hist = predHist[tid];
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while (!pred_hist.empty() &&
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pred_hist.front().seqNum > squashed_sn) {
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if (pred_hist.front().usedRAS) {
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i,"
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" target: %s.\n", tid,
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pred_hist.front().RASIndex, pred_hist.front().RASTarget);
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RAS[tid].restore(pred_hist.front().RASIndex,
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pred_hist.front().RASTarget);
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} else if(pred_hist.front().wasCall && pred_hist.front().validBTB) {
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// Was a call but predicated false. Pop RAS here
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DPRINTF(Fetch, "BranchPred: [tid: %i] Squashing"
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" Call [sn:%i] PC: %s Popping RAS\n", tid,
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pred_hist.front().seqNum, pred_hist.front().pc);
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RAS[tid].pop();
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}
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// This call should delete the bpHistory.
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BPSquash(pred_hist.front().bpHistory);
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing history for [sn:%i] "
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"PC %s.\n", tid, pred_hist.front().seqNum,
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pred_hist.front().pc);
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pred_hist.pop_front();
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DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n",
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tid, predHist[tid].size());
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
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const TheISA::PCState &corrTarget,
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bool actually_taken,
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ThreadID tid)
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{
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// Now that we know that a branch was mispredicted, we need to undo
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// all the branches that have been seen up until this branch and
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// fix up everything.
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// NOTE: This should be call conceivably in 2 scenarios:
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// (1) After an branch is executed, it updates its status in the ROB
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// The commit stage then checks the ROB update and sends a signal to
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// the fetch stage to squash history after the mispredict
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// (2) In the decode stage, you can find out early if a unconditional
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// PC-relative, branch was predicted incorrectly. If so, a signal
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// to the fetch stage is sent to squash history after the mispredict
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History &pred_hist = predHist[tid];
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++condIncorrect;
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Squashing from sequence number %i, "
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"setting target to %s.\n",
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tid, squashed_sn, corrTarget);
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// Squash All Branches AFTER this mispredicted branch
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squash(squashed_sn, tid);
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// If there's a squash due to a syscall, there may not be an entry
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// corresponding to the squash. In that case, don't bother trying to
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// fix up the entry.
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if (!pred_hist.empty()) {
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HistoryIt hist_it = pred_hist.begin();
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//HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(),
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// squashed_sn);
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//assert(hist_it != pred_hist.end());
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if (pred_hist.front().seqNum != squashed_sn) {
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DPRINTF(Fetch, "Front sn %i != Squash sn %i\n",
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pred_hist.front().seqNum, squashed_sn);
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assert(pred_hist.front().seqNum == squashed_sn);
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}
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if ((*hist_it).usedRAS) {
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++RASIncorrect;
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}
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BPUpdate((*hist_it).pc, actually_taken,
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pred_hist.front().bpHistory, true);
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if (actually_taken) {
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if (hist_it->wasReturn && !hist_it->usedRAS) {
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DPRINTF(Fetch, "BranchPred: [tid: %i] Incorrectly predicted"
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" return [sn:%i] PC: %s\n", tid, hist_it->seqNum,
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hist_it->pc);
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RAS[tid].pop();
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}
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DPRINTF(Fetch,"BranchPred: [tid: %i] BTB Update called for [sn:%i]"
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" PC: %s\n", tid,hist_it->seqNum, hist_it->pc);
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BTB.update((*hist_it).pc, corrTarget, tid);
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} else {
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//Actually not Taken
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if (hist_it->usedRAS) {
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DPRINTF(Fetch,"BranchPred: [tid: %i] Incorrectly predicted"
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" return [sn:%i] PC: %s Restoring RAS\n", tid,
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hist_it->seqNum, hist_it->pc);
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS"
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" to: %i, target: %s.\n", tid,
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hist_it->RASIndex, hist_it->RASTarget);
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RAS[tid].restore(hist_it->RASIndex, hist_it->RASTarget);
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} else if (hist_it->wasCall && hist_it->validBTB) {
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//Was a Call but predicated false. Pop RAS here
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DPRINTF(Fetch, "BranchPred: [tid: %i] Incorrectly predicted"
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" Call [sn:%i] PC: %s Popping RAS\n", tid,
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hist_it->seqNum, hist_it->pc);
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RAS[tid].pop();
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}
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}
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DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing history for [sn:%i]"
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" PC %s Actually Taken: %i\n", tid, hist_it->seqNum,
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hist_it->pc, actually_taken);
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pred_hist.erase(hist_it);
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DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid,
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predHist[tid].size());
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::BPUncond(void * &bp_history)
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{
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// Only the tournament predictor cares about unconditional branches.
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if (predictor == Tournament) {
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tournamentBP->uncondBr(bp_history);
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::BPSquash(void *bp_history)
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{
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if (predictor == Local) {
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localBP->squash(bp_history);
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} else if (predictor == Tournament) {
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tournamentBP->squash(bp_history);
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} else {
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panic("Predictor type is unexpected value!");
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}
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}
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template <class Impl>
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bool
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BPredUnit<Impl>::BPLookup(Addr instPC, void * &bp_history)
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{
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if (predictor == Local) {
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return localBP->lookup(instPC, bp_history);
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} else if (predictor == Tournament) {
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return tournamentBP->lookup(instPC, bp_history);
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} else {
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panic("Predictor type is unexpected value!");
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::BPBTBUpdate(Addr instPC, void * &bp_history)
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{
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if (predictor == Local) {
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return localBP->BTBUpdate(instPC, bp_history);
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} else if (predictor == Tournament) {
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return tournamentBP->BTBUpdate(instPC, bp_history);
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} else {
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panic("Predictor type is unexpected value!");
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::BPUpdate(Addr instPC, bool taken, void *bp_history,
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bool squashed)
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{
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if (predictor == Local) {
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localBP->update(instPC, taken, bp_history);
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} else if (predictor == Tournament) {
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tournamentBP->update(instPC, taken, bp_history, squashed);
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} else {
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panic("Predictor type is unexpected value!");
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}
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}
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template <class Impl>
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void
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BPredUnit<Impl>::dump()
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{
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HistoryIt pred_hist_it;
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for (int i = 0; i < Impl::MaxThreads; ++i) {
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if (!predHist[i].empty()) {
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pred_hist_it = predHist[i].begin();
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cprintf("predHist[%i].size(): %i\n", i, predHist[i].size());
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while (pred_hist_it != predHist[i].end()) {
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cprintf("[sn:%lli], PC:%#x, tid:%i, predTaken:%i, "
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"bpHistory:%#x\n",
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pred_hist_it->seqNum, pred_hist_it->pc,
|
|
pred_hist_it->tid, pred_hist_it->predTaken,
|
|
pred_hist_it->bpHistory);
|
|
pred_hist_it++;
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|
|
}
|
|
}
|