d2b57a7473
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
469 lines
53 KiB
Text
469 lines
53 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.274137 # Number of seconds simulated
|
|
sim_ticks 274137453500 # Number of ticks simulated
|
|
final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 134061 # Simulator instruction rate (inst/s)
|
|
host_op_rate 134061 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 61063086 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 219148 # Number of bytes of host memory used
|
|
host_seconds 4489.41 # Real time elapsed on the host
|
|
sim_insts 601856964 # Number of instructions simulated
|
|
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 57024 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 114518787 # DTB read hits
|
|
system.cpu.dtb.read_misses 2631 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 114521418 # DTB read accesses
|
|
system.cpu.dtb.write_hits 39662426 # DTB write hits
|
|
system.cpu.dtb.write_misses 2302 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 39664728 # DTB write accesses
|
|
system.cpu.dtb.data_hits 154181213 # DTB hits
|
|
system.cpu.dtb.data_misses 4933 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 154186146 # DTB accesses
|
|
system.cpu.itb.fetch_hits 25086764 # ITB hits
|
|
system.cpu.itb.fetch_misses 22 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 25086786 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
system.cpu.numCycles 548274908 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups
|
|
system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted
|
|
system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect
|
|
system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups
|
|
system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits
|
|
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
|
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
|
system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage
|
|
system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 155050348 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 89.213788 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
|
system.cpu.comStores 39451321 # Number of Store instructions committed
|
|
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
|
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
|
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 30 # number of replacements
|
|
system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 25085741 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1021 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 451299 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 152406041 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1559322 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 436902 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 917 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 430079 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 430093 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4120 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4961 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21196 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21196 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 25316 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 26157 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 891 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 891 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4120 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4961 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21196 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21196 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 25316 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 26157 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|