506 lines
56 KiB
Text
506 lines
56 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.145301 # Number of seconds simulated
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sim_ticks 145300717500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 109615 # Simulator instruction rate (inst/s)
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host_tick_rate 28162171 # Simulator tick rate (ticks/s)
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host_mem_usage 246532 # Number of bytes of host memory used
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host_seconds 5159.43 # Real time elapsed on the host
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sim_insts 565552443 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 125840781 # DTB read hits
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system.cpu.dtb.read_misses 26740 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 125867521 # DTB read accesses
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system.cpu.dtb.write_hits 41455603 # DTB write hits
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system.cpu.dtb.write_misses 32148 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 41487751 # DTB write accesses
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system.cpu.dtb.data_hits 167296384 # DTB hits
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system.cpu.dtb.data_misses 58888 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 167355272 # DTB accesses
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system.cpu.itb.fetch_hits 71694847 # ITB hits
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system.cpu.itb.fetch_misses 40 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 71694887 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 290601436 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 36 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 451150539 72.57% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 7830 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.57% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 128375845 20.65% 93.23% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 42115665 6.77% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 621649928 # Type of FU issued
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system.cpu.iq.rate 2.139184 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 5190490 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.008350 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 1539391263 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 723910400 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 609602063 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 3418 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 1948 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 626838696 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 11620337 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 17312357 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 134964 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 365628 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 4436658 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 5886 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 50751 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 13016656 # Number of cycles IEW is squashing
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system.cpu.iew.iewBlockCycles 1515186 # Number of cycles IEW is blocking
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system.cpu.iew.iewUnblockCycles 101274 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispatchedInsts 690779591 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispSquashedInsts 2446688 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispLoadInsts 131826399 # Number of dispatched load instructions
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system.cpu.iew.iewDispStoreInsts 43887979 # Number of dispatched store instructions
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system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewIQFullEvents 41001 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewLSQFullEvents 13794 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.memOrderViolationEvents 365628 # Number of memory order violations
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system.cpu.iew.predictedTakenIncorrect 4028203 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 602481 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 4630684 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 613929253 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 125867602 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 7720675 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 45600120 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 167374804 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 68499674 # Number of branches executed
|
|
system.cpu.iew.exec_stores 41507202 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.112616 # Inst execution rate
|
|
system.cpu.iew.wb_sent 611080780 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 609603660 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 419952220 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 531843575 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.097731 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.789616 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 88769206 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 4122409 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 277515436 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.168733 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.607930 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 91720629 33.05% 33.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 75337959 27.15% 60.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 31629889 11.40% 71.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 9762168 3.52% 75.11% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 10089201 3.64% 78.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 21364718 7.70% 86.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 5897222 2.13% 88.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 2300204 0.83% 89.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 29413446 10.60% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 277515436 # Number of insts commited each cycle
|
|
system.cpu.commit.count 601856963 # Number of instructions committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 153965363 # Number of memory references committed
|
|
system.cpu.commit.loads 114514042 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 62547159 # Number of branches committed
|
|
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 29413446 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 938663770 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1394275800 # The number of ROB writes
|
|
system.cpu.timesIdled 2250 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 69344 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.513836 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.513836 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.946145 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.946145 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 864545189 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 501712619 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 277 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 57 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 36 # number of replacements
|
|
system.cpu.icache.tagsinuse 798.939045 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 71693570 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 940 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 76269.755319 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::0 798.939045 # Average occupied blocks per context
|
|
system.cpu.icache.occ_percent::0 0.390107 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits 71693570 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits 71693570 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits 71693570 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses 1277 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency 46025000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency 46025000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency 46025000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses 71694847 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses 71694847 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses 71694847 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency 36041.503524 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency 36041.503524 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency 36041.503524 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses 940 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses 940 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses 940 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 33513000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency 33513000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency 33513000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 470805 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4093.951768 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 151630549 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 474901 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 319.288755 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 126064000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::0 4093.951768 # Average occupied blocks per context
|
|
system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits 113482808 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits 38147738 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits 151630546 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits 151630546 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses 730789 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses 1303583 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses 2034372 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses 2034372 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency 11799719000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency 19632109224 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency 31431828224 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency 31431828224 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses 114213597 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses 153664918 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses 153664918 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate 0.033043 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate 0.013239 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate 0.013239 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency 15450.383816 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency 15450.383816 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 917496 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 119 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7710.050420 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks 423137 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits 511918 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits 1047553 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits 1559471 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits 1559471 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses 218871 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses 256030 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses 474901 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses 474901 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1640511500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3027783994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency 4668295494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency 4668295494 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7495.335152 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 74456 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 17669.602101 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 478138 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 90356 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 5.291713 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::0 1747.606056 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 15921.996045 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_percent::0 0.053333 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::1 0.485901 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits 186860 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits 423137 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits 196226 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits 383086 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits 383086 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses 32951 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses 92755 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses 92755 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency 1133426500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2066052500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency 3199479000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency 3199479000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses 219811 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses 423137 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses 256030 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses 475841 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses 475841 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.149906 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.233582 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate 0.194929 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate 0.194929 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency 34493.870950 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency 34493.870950 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 468000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 80 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5850 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks 59325 # number of writebacks
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32951 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses 92755 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses 92755 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1022116000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877697000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2899813000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2899813000 # number of overall MSHR miss cycles
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|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149906 # mshr miss rate for ReadReq accesses
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|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233582 # mshr miss rate for ReadExReq accesses
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|
system.cpu.l2cache.demand_mshr_miss_rate 0.194929 # mshr miss rate for demand accesses
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|
system.cpu.l2cache.overall_mshr_miss_rate 0.194929 # mshr miss rate for overall accesses
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|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency
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|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
|
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---------- End Simulation Statistics ----------
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