gem5/src/mem/cache
Steve Reinhardt 884807a68a Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work.  Timing is closer but not there yet.

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extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15 20:11:06 -07:00
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miss Fix up a few statistics problems. 2007-06-30 13:34:16 -07:00
prefetch Getting closer... 2007-06-21 11:59:17 -07:00
tags Add CacheRepl trace flag and move a couple DPRINTFs to it. 2007-07-14 13:28:52 -07:00
base_cache.cc Fix up a few statistics problems. 2007-06-30 13:34:16 -07:00
base_cache.hh Move a couple of DPRINTFs from Cache to CachePort. 2007-07-14 13:16:58 -07:00
BaseCache.py Get rid of remaining traces of obsolete CoherenceProtocol object. 2007-06-30 17:59:45 -07:00
cache.cc Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache.hh Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache_blk.hh More major reorg of cache. Seems to work for atomic mode now, 2007-06-17 17:27:53 -07:00
cache_builder.cc Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache_impl.hh Fix up a bunch of multilevel coherence issues. 2007-07-15 20:11:06 -07:00
SConscript Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00