86777c9db1
TimingSimpleCPU. Not there yet.
cpu/simple/atomic.cc:
Only read SC result if store was an SC.
Don't fake SC here; fake it in PhysicalMemory so
all CPU models can share in the joy.
cpu/simple/timing.cc:
Don't forget to checkForInterrupts().
Only fetch subsequent instruction if we're still running
(i.e. not quiesced).
dev/io_device.hh:
Initialize port pointer in SendEvent object.
mem/physical.cc:
Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
Initialize flags to all clear, not uninitialized.
Otherwise we can't reliably look at flags w/o explicitly
setting them every time we create a request.
--HG--
extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6
570 lines
15 KiB
C++
570 lines
15 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/utility.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/simple/timing.hh"
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#include "mem/packet_impl.hh"
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#include "sim/builder.hh"
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using namespace std;
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using namespace TheISA;
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void
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TimingSimpleCPU::init()
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{
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//Create Memory Ports (conect them up)
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Port *mem_dport = mem->getPort("");
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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Port *mem_iport = mem->getPort("");
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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BaseCPU::init();
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#if FULL_SYSTEM
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(xc, xc->readCpuId());
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}
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#endif
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}
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Tick
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TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
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{
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panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
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return curTick;
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}
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void
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TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
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{
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panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
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}
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void
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TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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return;
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panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
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}
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TimingSimpleCPU::TimingSimpleCPU(Params *p)
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: BaseSimpleCPU(p), icachePort(this), dcachePort(this)
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{
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_status = Idle;
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ifetch_pkt = dcache_pkt = NULL;
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}
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TimingSimpleCPU::~TimingSimpleCPU()
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{
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}
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void
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TimingSimpleCPU::serialize(ostream &os)
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{
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BaseSimpleCPU::serialize(os);
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SERIALIZE_ENUM(_status);
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}
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void
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TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseSimpleCPU::unserialize(cp, section);
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UNSERIALIZE_ENUM(_status);
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}
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void
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TimingSimpleCPU::switchOut(Sampler *s)
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{
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sampler = s;
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if (status() == Running) {
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_status = SwitchedOut;
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}
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sampler->signalSwitched();
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}
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void
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TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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// if any of this CPU's ExecContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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break;
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}
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}
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}
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void
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TimingSimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(cpuXC);
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assert(_status == Idle);
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notIdleFraction++;
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_status = Running;
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// kick things off by initiating the fetch of the next instruction
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Event *e =
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new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
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e->schedule(curTick + cycles(delay));
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}
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void
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TimingSimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(cpuXC);
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panic("TimingSimpleCPU::suspendContext not implemented");
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assert(_status == Running);
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notIdleFraction--;
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_status = Idle;
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}
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template <class T>
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Fault
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TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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Request *data_read_req = new Request(true);
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data_read_req->setVaddr(addr);
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data_read_req->setSize(sizeof(T));
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data_read_req->setFlags(flags);
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data_read_req->setTime(curTick);
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if (traceData) {
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traceData->setAddr(data_read_req->getVaddr());
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}
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// translate to physical address
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Fault fault = cpuXC->translateDataReadReq(data_read_req);
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// Now do the access.
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if (fault == NoFault) {
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Packet *data_read_pkt = new Packet;
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data_read_pkt->cmd = Read;
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data_read_pkt->req = data_read_req;
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data_read_pkt->dataDynamic<T>(new T);
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data_read_pkt->addr = data_read_req->getPaddr();
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data_read_pkt->size = sizeof(T);
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data_read_pkt->dest = Packet::Broadcast;
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if (!dcachePort.sendTiming(data_read_pkt)) {
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_status = DcacheRetry;
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dcache_pkt = data_read_pkt;
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} else {
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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}
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}
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// This will need a new way to tell if it has a dcache attached.
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if (data_read_req->getFlags() & UNCACHEABLE)
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recordEvent("Uncached Read");
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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Request *data_write_req = new Request(true);
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data_write_req->setVaddr(addr);
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data_write_req->setTime(curTick);
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data_write_req->setSize(sizeof(T));
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data_write_req->setFlags(flags);
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// translate to physical address
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Fault fault = cpuXC->translateDataWriteReq(data_write_req);
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// Now do the access.
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if (fault == NoFault) {
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Packet *data_write_pkt = new Packet;
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data_write_pkt->cmd = Write;
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data_write_pkt->req = data_write_req;
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data_write_pkt->allocate();
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data_write_pkt->size = sizeof(T);
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data_write_pkt->set(data);
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data_write_pkt->addr = data_write_req->getPaddr();
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data_write_pkt->dest = Packet::Broadcast;
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if (!dcachePort.sendTiming(data_write_pkt)) {
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_status = DcacheRetry;
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dcache_pkt = data_write_pkt;
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} else {
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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}
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}
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (data_write_req->getFlags() & UNCACHEABLE)
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recordEvent("Uncached Write");
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// If the write needs to have a fault on the access, consider calling
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// changeStatus() and changing it to "bad addr write" or something.
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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TimingSimpleCPU::write(uint64_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint32_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint16_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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TimingSimpleCPU::write(uint8_t data, Addr addr,
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unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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void
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TimingSimpleCPU::fetch()
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{
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checkForInterrupts();
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Request *ifetch_req = new Request(true);
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ifetch_req->setSize(sizeof(MachInst));
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ifetch_pkt = new Packet;
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ifetch_pkt->cmd = Read;
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ifetch_pkt->dataStatic(&inst);
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ifetch_pkt->req = ifetch_req;
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ifetch_pkt->size = sizeof(MachInst);
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ifetch_pkt->dest = Packet::Broadcast;
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Fault fault = setupFetchPacket(ifetch_pkt);
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if (fault == NoFault) {
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if (!icachePort.sendTiming(ifetch_pkt)) {
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// Need to wait for retry
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_status = IcacheRetry;
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} else {
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// Need to wait for cache to respond
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_status = IcacheWaitResponse;
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// ownership of packet transferred to memory system
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ifetch_pkt = NULL;
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}
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} else {
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panic("TimingSimpleCPU fetch fault handling not implemented");
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}
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}
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void
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TimingSimpleCPU::completeInst(Fault fault)
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{
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postExecute();
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if (traceData) {
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traceData->finalize();
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}
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advancePC(fault);
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if (_status == Running) {
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// kick off fetch of next instruction... callback from icache
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// response will cause that instruction to be executed,
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// keeping the CPU running.
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fetch();
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}
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}
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void
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TimingSimpleCPU::completeIfetch()
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{
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// received a response from the icache: execute the received
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// instruction
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assert(_status == IcacheWaitResponse);
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_status = Running;
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preExecute();
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if (curStaticInst->isMemRef()) {
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// load or store: just send to dcache
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Fault fault = curStaticInst->initiateAcc(this, traceData);
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assert(fault == NoFault);
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assert(_status == DcacheWaitResponse);
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// instruction will complete in dcache response callback
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} else {
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// non-memory instruction: execute completely now
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Fault fault = curStaticInst->execute(this, traceData);
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completeInst(fault);
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}
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}
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bool
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TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
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{
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cpu->completeIfetch();
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return true;
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}
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Packet *
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TimingSimpleCPU::IcachePort::recvRetry()
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{
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// we shouldn't get a retry unless we have a packet that we're
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// waiting to transmit
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assert(cpu->ifetch_pkt != NULL);
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assert(cpu->_status == IcacheRetry);
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cpu->_status = IcacheWaitResponse;
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Packet *tmp = cpu->ifetch_pkt;
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cpu->ifetch_pkt = NULL;
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return tmp;
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}
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void
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TimingSimpleCPU::completeDataAccess(Packet *pkt)
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{
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// received a response from the dcache: complete the load or store
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// instruction
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assert(pkt->result == Success);
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assert(_status == DcacheWaitResponse);
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_status = Running;
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Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
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completeInst(fault);
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}
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bool
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TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
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{
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cpu->completeDataAccess(pkt);
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return true;
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}
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Packet *
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TimingSimpleCPU::DcachePort::recvRetry()
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{
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// we shouldn't get a retry unless we have a packet that we're
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// waiting to transmit
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assert(cpu->dcache_pkt != NULL);
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assert(cpu->_status == DcacheRetry);
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cpu->_status = DcacheWaitResponse;
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Packet *tmp = cpu->dcache_pkt;
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cpu->dcache_pkt = NULL;
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return tmp;
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}
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////////////////////////////////////////////////////////////////////////
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//
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// TimingSimpleCPU Simulation Object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
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Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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SimObjectParam<MemObject *> mem;
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#if FULL_SYSTEM
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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Param<Tick> profile;
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#else
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SimObjectParam<Process *> workload;
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#endif // FULL_SYSTEM
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Param<int> clock;
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Param<bool> defer_registration;
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Param<int> width;
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Param<bool> function_trace;
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Param<Tick> function_trace_start;
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Param<bool> simulate_stalls;
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END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
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INIT_PARAM(max_insts_any_thread,
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"terminate when any thread reaches this inst count"),
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INIT_PARAM(max_insts_all_threads,
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"terminate when all threads have reached this inst count"),
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INIT_PARAM(max_loads_any_thread,
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"terminate when any thread reaches this load count"),
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INIT_PARAM(max_loads_all_threads,
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"terminate when all threads have reached this load count"),
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INIT_PARAM(mem, "memory"),
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#if FULL_SYSTEM
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INIT_PARAM(itb, "Instruction TLB"),
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INIT_PARAM(dtb, "Data TLB"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(profile, ""),
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#else
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INIT_PARAM(workload, "processes to run"),
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#endif // FULL_SYSTEM
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
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INIT_PARAM(width, "cpu width"),
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INIT_PARAM(function_trace, "Enable function trace"),
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INIT_PARAM(function_trace_start, "Cycle to start function trace"),
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INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
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END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
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CREATE_SIM_OBJECT(TimingSimpleCPU)
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{
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TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
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params->name = getInstanceName();
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params->numberOfThreads = 1;
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params->max_insts_any_thread = max_insts_any_thread;
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params->max_insts_all_threads = max_insts_all_threads;
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params->max_loads_any_thread = max_loads_any_thread;
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
params->deferRegistration = defer_registration;
|
|
params->clock = clock;
|
|
params->functionTrace = function_trace;
|
|
params->functionTraceStart = function_trace_start;
|
|
params->mem = mem;
|
|
|
|
#if FULL_SYSTEM
|
|
params->itb = itb;
|
|
params->dtb = dtb;
|
|
params->system = system;
|
|
params->cpu_id = cpu_id;
|
|
params->profile = profile;
|
|
#else
|
|
params->process = workload;
|
|
#endif
|
|
|
|
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
|
|
|