86777c9db1
TimingSimpleCPU. Not there yet. cpu/simple/atomic.cc: Only read SC result if store was an SC. Don't fake SC here; fake it in PhysicalMemory so all CPU models can share in the joy. cpu/simple/timing.cc: Don't forget to checkForInterrupts(). Only fetch subsequent instruction if we're still running (i.e. not quiesced). dev/io_device.hh: Initialize port pointer in SendEvent object. mem/physical.cc: Move fake SC "implementation" here from AtomicSimpleCPU. mem/request.hh: Initialize flags to all clear, not uninitialized. Otherwise we can't reliably look at flags w/o explicitly setting them every time we create a request. --HG-- extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6 |
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.. | ||
memtest | ||
o3 | ||
ozone | ||
simple | ||
trace | ||
base.cc | ||
base.hh | ||
base_dyn_inst.cc | ||
base_dyn_inst.hh | ||
cpu_exec_context.cc | ||
cpu_exec_context.hh | ||
cpu_models.py | ||
exec_context.hh | ||
exetrace.cc | ||
exetrace.hh | ||
inst_seq.hh | ||
intr_control.cc | ||
intr_control.hh | ||
op_class.cc | ||
op_class.hh | ||
pc_event.cc | ||
pc_event.hh | ||
profile.cc | ||
profile.hh | ||
SConscript | ||
smt.hh | ||
static_inst.cc | ||
static_inst.hh |