a91ee5abc2
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa. Now it's back to just debugging execution of code for the release (those unaligned memory access instruction pairs are still quite the pain i might add) arch/mips/isa_traits.hh: declare functions for .cc file arch/mips/isa_traits.cc: delete unnecessary overloaded functions implement condition code functions implement round function arch/mips/isa/base.isa: remove R31 constant... define in the operands.isa file instead arch/mips/isa/decoder.isa: wholesale changes once again to FP. Now the FP Condition Codes are implemented and the FP programs can run and complete to finish. Use isnan() instead of my unorderedFP() function Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand arch/mips/isa/operands.isa: add more operands for special control regs in int and FP regfiles arch/mips/isa/formats/branch.isa: use R31 instead of r31 arch/mips/isa/formats/fp.isa: use MakeCCVector to set Condition Codes in FCSR arch/mips/regfile/float_regfile.hh: treat control regs like any other reg. Just Index them after the regular architectural registers arch/mips/regfile/int_regfile.hh: treat hi,lo as regular int. regs w/special indexing arch/mips/regfile/regfile.hh: no longer need for special register accesses with their own function. --HG-- rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e
229 lines
6.2 KiB
C++
229 lines
6.2 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/mips/isa_traits.hh"
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#include "config/full_system.hh"
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#include "cpu/static_inst.hh"
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#include "sim/serialize.hh"
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#include "base/bitfield.hh"
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using namespace MipsISA;
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using namespace std;
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void
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MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
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{
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/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
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uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
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lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
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lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
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#if FULL_SYSTEM
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copyIprs(xc);
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#endif*/
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}
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void
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MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
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{
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/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
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uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
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lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
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lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
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#endif*/
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}
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uint64_t
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MipsISA::fpConvert(double fp_val, ConvertType cvt_type)
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{
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switch (cvt_type)
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{
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case SINGLE_TO_DOUBLE:
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double sdouble_val = fp_val;
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void *sdouble_ptr = &sdouble_val;
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uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
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return sdp_bits;
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case SINGLE_TO_WORD:
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int32_t sword_val = (int32_t) fp_val;
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void *sword_ptr = &sword_val;
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uint64_t sword_bits= *(uint32_t *) sword_ptr;
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return sword_bits;
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case WORD_TO_SINGLE:
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float wfloat_val = fp_val;
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void *wfloat_ptr = &wfloat_val;
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uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
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return wfloat_bits;
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case WORD_TO_DOUBLE:
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double wdouble_val = fp_val;
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void *wdouble_ptr = &wdouble_val;
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uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
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return wdp_bits;
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default:
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panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
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return 0;
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}
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}
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double
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MipsISA::roundFP(double val, int digits)
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{
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double digit_offset = pow(10.0,digits);
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val = val * digit_offset;
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val = val + 0.5;
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val = floor(val);
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val = val / digit_offset;
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return val;
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}
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double
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MipsISA::truncFP(double val)
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{
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int trunc_val = (int) val;
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return (double) trunc_val;
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}
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bool
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MipsISA::getFPConditionCode(uint32_t fcsr_reg, int cc)
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{
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//uint32_t cc_bits = xc->readFloatReg(35);
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return false;//regFile.floatRegfile.getConditionCode(cc);
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}
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uint32_t
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MipsISA::makeCCVector(uint32_t fcsr, int num, bool val)
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{
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int shift = (num == 0) ? 22 : num + 23;
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fcsr = fcsr | (val << shift);
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return fcsr;
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}
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#if FULL_SYSTEM
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static inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(MipsISA::PageBytes - 1); }
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static inline Addr
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RoundPage(Addr addr)
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{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
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#endif
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void
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IntRegFile::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(regs, NumIntRegs);
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}
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void
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IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(regs, NumIntRegs);
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}
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void
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RegFile::serialize(std::ostream &os)
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{
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intRegFile.serialize(os);
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//SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
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//SERIALIZE_SCALAR(miscRegs.fpcr);
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//SERIALIZE_SCALAR(miscRegs.uniq);
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//SERIALIZE_SCALAR(miscRegs.lock_flag);
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//SERIALIZE_SCALAR(miscRegs.lock_addr);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(nnpc);
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#if FULL_SYSTEM
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SERIALIZE_ARRAY(palregs, NumIntRegs);
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SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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SERIALIZE_SCALAR(intrflag);
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SERIALIZE_SCALAR(pal_shadow);
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#endif
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}
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void
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RegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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intRegFile.unserialize(cp, section);
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//UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
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//UNSERIALIZE_SCALAR(miscRegs.fpcr);
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//UNSERIALIZE_SCALAR(miscRegs.uniq);
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//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
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//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(nnpc);
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#if FULL_SYSTEM
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UNSERIALIZE_ARRAY(palregs, NumIntRegs);
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UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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UNSERIALIZE_SCALAR(intrflag);
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UNSERIALIZE_SCALAR(pal_shadow);
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#endif
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}
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#if FULL_SYSTEM
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void
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PTE::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(tag);
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SERIALIZE_SCALAR(ppn);
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SERIALIZE_SCALAR(xre);
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SERIALIZE_SCALAR(xwe);
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SERIALIZE_SCALAR(asn);
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SERIALIZE_SCALAR(asma);
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SERIALIZE_SCALAR(fonr);
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SERIALIZE_SCALAR(fonw);
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SERIALIZE_SCALAR(valid);
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}
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void
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PTE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(tag);
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UNSERIALIZE_SCALAR(ppn);
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UNSERIALIZE_SCALAR(xre);
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UNSERIALIZE_SCALAR(xwe);
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UNSERIALIZE_SCALAR(asn);
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UNSERIALIZE_SCALAR(asma);
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UNSERIALIZE_SCALAR(fonr);
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UNSERIALIZE_SCALAR(fonw);
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UNSERIALIZE_SCALAR(valid);
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}
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#endif //FULL_SYSTEM
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