1119 lines
34 KiB
Text
1119 lines
34 KiB
Text
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 1234
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randomization: 0
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tech_nm: 45
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freq_mhz: 3000
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block_size_bytes: 64
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block_size_bits: 6
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memory_size_bytes: 1073741824
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memory_size_bits: 30
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DMA_Controller config: DMAController_0
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version: 0
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buffer_size: 32
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dma_sequencer: DMASequencer_0
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number_of_TBEs: 256
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recycle_latency: 10
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request_latency: 6
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transitions_per_cycle: 32
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Directory_Controller config: DirectoryController_0
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version: 0
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buffer_size: 32
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directory_latency: 6
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directory_name: DirectoryMemory_0
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dma_select_low_bit: 6
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dma_select_num_bits: 0
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memory_controller_name: MemoryControl_0
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number_of_TBEs: 256
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recycle_latency: 10
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_0
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version: 0
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buffer_size: 32
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cache: l1u_0
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_0
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_1
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version: 1
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buffer_size: 32
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cache: l1u_1
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_1
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_2
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version: 2
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buffer_size: 32
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cache: l1u_2
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_2
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_3
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version: 3
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buffer_size: 32
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cache: l1u_3
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_3
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_4
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version: 4
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buffer_size: 32
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cache: l1u_4
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_4
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_5
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version: 5
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buffer_size: 32
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cache: l1u_5
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_5
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_6
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version: 6
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buffer_size: 32
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cache: l1u_6
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_6
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_7
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version: 7
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buffer_size: 32
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cache: l1u_7
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_7
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transitions_per_cycle: 32
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Cache config: l1u_0
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controller: L1CacheController_0
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_1
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controller: L1CacheController_1
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_2
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controller: L1CacheController_2
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_3
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controller: L1CacheController_3
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_4
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controller: L1CacheController_4
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_5
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controller: L1CacheController_5
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_6
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controller: L1CacheController_6
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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Cache config: l1u_7
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controller: L1CacheController_7
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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DirectoryMemory Global Config:
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number of directory memories: 1
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total memory size bytes: 1073741824
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total memory size bits: 30
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DirectoryMemory module config: DirectoryMemory_0
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controller: DirectoryController_0
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version: 0
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memory_bits: 30
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memory_size_bytes: 1073741824
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memory_size_Kbytes: 1.04858e+06
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memory_size_Mbytes: 1024
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memory_size_Gbytes: 1
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Seqeuncer config: Sequencer_0
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controller: L1CacheController_0
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version: 0
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_1
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controller: L1CacheController_1
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version: 1
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_2
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controller: L1CacheController_2
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version: 2
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_3
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controller: L1CacheController_3
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version: 3
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_4
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controller: L1CacheController_4
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version: 4
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_5
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controller: L1CacheController_5
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version: 5
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_6
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controller: L1CacheController_6
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version: 6
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Seqeuncer config: Sequencer_7
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controller: L1CacheController_7
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version: 7
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology: theTopology
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virtual_net_0: active, ordered
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virtual_net_1: active, ordered
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virtual_net_2: active, ordered
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virtual_net_3: inactive
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virtual_net_4: active, ordered
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virtual_net_5: active, ordered
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--- Begin Topology Print ---
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Topology print ONLY indicates the _NETWORK_ latency between two machines
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It does NOT include the latency within the machines
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L1Cache-0 Network Latencies
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L1Cache-0 -> L1Cache-1 net_lat: 7
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L1Cache-0 -> L1Cache-2 net_lat: 7
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L1Cache-0 -> L1Cache-3 net_lat: 7
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L1Cache-0 -> L1Cache-4 net_lat: 7
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L1Cache-0 -> L1Cache-5 net_lat: 7
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L1Cache-0 -> L1Cache-6 net_lat: 7
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L1Cache-0 -> L1Cache-7 net_lat: 7
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L1Cache-0 -> Directory-0 net_lat: 7
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L1Cache-0 -> DMA-0 net_lat: 7
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L1Cache-1 Network Latencies
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L1Cache-1 -> L1Cache-0 net_lat: 7
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L1Cache-1 -> L1Cache-2 net_lat: 7
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L1Cache-1 -> L1Cache-3 net_lat: 7
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L1Cache-1 -> L1Cache-4 net_lat: 7
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L1Cache-1 -> L1Cache-5 net_lat: 7
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L1Cache-1 -> L1Cache-6 net_lat: 7
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L1Cache-1 -> L1Cache-7 net_lat: 7
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L1Cache-1 -> Directory-0 net_lat: 7
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L1Cache-1 -> DMA-0 net_lat: 7
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L1Cache-2 Network Latencies
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L1Cache-2 -> L1Cache-0 net_lat: 7
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L1Cache-2 -> L1Cache-1 net_lat: 7
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L1Cache-2 -> L1Cache-3 net_lat: 7
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L1Cache-2 -> L1Cache-4 net_lat: 7
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L1Cache-2 -> L1Cache-5 net_lat: 7
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L1Cache-2 -> L1Cache-6 net_lat: 7
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L1Cache-2 -> L1Cache-7 net_lat: 7
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L1Cache-2 -> Directory-0 net_lat: 7
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L1Cache-2 -> DMA-0 net_lat: 7
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L1Cache-3 Network Latencies
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L1Cache-3 -> L1Cache-0 net_lat: 7
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L1Cache-3 -> L1Cache-1 net_lat: 7
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L1Cache-3 -> L1Cache-2 net_lat: 7
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L1Cache-3 -> L1Cache-4 net_lat: 7
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L1Cache-3 -> L1Cache-5 net_lat: 7
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L1Cache-3 -> L1Cache-6 net_lat: 7
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L1Cache-3 -> L1Cache-7 net_lat: 7
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L1Cache-3 -> Directory-0 net_lat: 7
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L1Cache-3 -> DMA-0 net_lat: 7
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L1Cache-4 Network Latencies
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L1Cache-4 -> L1Cache-0 net_lat: 7
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L1Cache-4 -> L1Cache-1 net_lat: 7
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L1Cache-4 -> L1Cache-2 net_lat: 7
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L1Cache-4 -> L1Cache-3 net_lat: 7
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L1Cache-4 -> L1Cache-5 net_lat: 7
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L1Cache-4 -> L1Cache-6 net_lat: 7
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L1Cache-4 -> L1Cache-7 net_lat: 7
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L1Cache-4 -> Directory-0 net_lat: 7
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L1Cache-4 -> DMA-0 net_lat: 7
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L1Cache-5 Network Latencies
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L1Cache-5 -> L1Cache-0 net_lat: 7
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L1Cache-5 -> L1Cache-1 net_lat: 7
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L1Cache-5 -> L1Cache-2 net_lat: 7
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L1Cache-5 -> L1Cache-3 net_lat: 7
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L1Cache-5 -> L1Cache-4 net_lat: 7
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L1Cache-5 -> L1Cache-6 net_lat: 7
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L1Cache-5 -> L1Cache-7 net_lat: 7
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L1Cache-5 -> Directory-0 net_lat: 7
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L1Cache-5 -> DMA-0 net_lat: 7
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L1Cache-6 Network Latencies
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L1Cache-6 -> L1Cache-0 net_lat: 7
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L1Cache-6 -> L1Cache-1 net_lat: 7
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L1Cache-6 -> L1Cache-2 net_lat: 7
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L1Cache-6 -> L1Cache-3 net_lat: 7
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L1Cache-6 -> L1Cache-4 net_lat: 7
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L1Cache-6 -> L1Cache-5 net_lat: 7
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L1Cache-6 -> L1Cache-7 net_lat: 7
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L1Cache-6 -> Directory-0 net_lat: 7
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L1Cache-6 -> DMA-0 net_lat: 7
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L1Cache-7 Network Latencies
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L1Cache-7 -> L1Cache-0 net_lat: 7
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L1Cache-7 -> L1Cache-1 net_lat: 7
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L1Cache-7 -> L1Cache-2 net_lat: 7
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L1Cache-7 -> L1Cache-3 net_lat: 7
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L1Cache-7 -> L1Cache-4 net_lat: 7
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L1Cache-7 -> L1Cache-5 net_lat: 7
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L1Cache-7 -> L1Cache-6 net_lat: 7
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L1Cache-7 -> Directory-0 net_lat: 7
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L1Cache-7 -> DMA-0 net_lat: 7
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Directory-0 Network Latencies
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Directory-0 -> L1Cache-0 net_lat: 7
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Directory-0 -> L1Cache-1 net_lat: 7
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Directory-0 -> L1Cache-2 net_lat: 7
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Directory-0 -> L1Cache-3 net_lat: 7
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Directory-0 -> L1Cache-4 net_lat: 7
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Directory-0 -> L1Cache-5 net_lat: 7
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Directory-0 -> L1Cache-6 net_lat: 7
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Directory-0 -> L1Cache-7 net_lat: 7
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Directory-0 -> DMA-0 net_lat: 7
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DMA-0 Network Latencies
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DMA-0 -> L1Cache-0 net_lat: 7
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DMA-0 -> L1Cache-1 net_lat: 7
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DMA-0 -> L1Cache-2 net_lat: 7
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DMA-0 -> L1Cache-3 net_lat: 7
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DMA-0 -> L1Cache-4 net_lat: 7
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DMA-0 -> L1Cache-5 net_lat: 7
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DMA-0 -> L1Cache-6 net_lat: 7
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DMA-0 -> L1Cache-7 net_lat: 7
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DMA-0 -> Directory-0 net_lat: 7
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--- End Topology Print ---
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Aug/05/2009 14:05:27
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 1657
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Elapsed_time_in_minutes: 27.6167
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Elapsed_time_in_hours: 0.460278
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Elapsed_time_in_days: 0.0191782
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Virtual_time_in_seconds: 1574.85
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Virtual_time_in_minutes: 26.2475
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Virtual_time_in_hours: 0.437458
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Virtual_time_in_days: 0.0182274
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Ruby_current_time: 31871403
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Ruby_start_time: 1
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Ruby_cycles: 31871402
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mbytes_resident: 150.73
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mbytes_total: 1502.58
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resident_ratio: 0.10032
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Total_misses: 0
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total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
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user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
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supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
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ruby_cycles_executed: 254971224 [ 31871403 31871403 31871403 31871403 31871403 31871403 31871403 31871403 ]
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transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
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transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
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cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
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misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
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Memory control MemoryControl_0:
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memory_total_requests: 1389969
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memory_reads: 695049
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memory_writes: 694795
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memory_refreshes: 66399
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memory_total_request_delays: 426018769
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memory_delays_per_request: 306.495
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memory_delays_in_input_queue: 90894877
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memory_delays_behind_head_of_bank_queue: 255108229
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memory_delays_stalled_at_head_of_bank_queue: 80015663
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memory_stalls_for_bank_busy: 12108953
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memory_stalls_for_random_busy: 0
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memory_stalls_for_anti_starvation: 24487499
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memory_stalls_for_arbitration: 15539710
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memory_stalls_for_bus: 20434932
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memory_stalls_for_tfaw: 0
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memory_stalls_for_read_write_turnaround: 6003845
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memory_stalls_for_read_read_turnaround: 1440724
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accesses_per_bank: 43357 44015 43781 43810 43753 43615 43533 43621 43760 43473 43392 43592 43408 43516 43431 43583 43408 43238 43387 43265 43461 43404 43268 43371 43341 43146 43143 43177 43023 43329 42971 43397
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Busy Controller Counts:
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L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:2
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Directory-0:0
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DMA-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 16 count: 749091 average: 11.7606 | standard deviation: 3.43055 | 0 1195 3094 5987 10211 16213 24379 33889 44818 55183 63828 70245 72985 71727 68120 64568 142649 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
|
|
miss_latency: [binsize: 128 max: 21143 count: 748999 average: 3853.8 | standard deviation: 2347.14 | 21685 2046 3724 6754 8786 8411 7788 8757 10178 12006 13478 13800 12395 13185 16353 16995 16436 16328 17286 17295 16892 18651 19670 16684 16291 17758 18049 16416 15965 16404 15524 14164 14431 15506 13589 12027 13053 13566 11578 10619 11289 11140 9536 9219 10023 9112 7727 7948 8409 7483 6331 6838 6701 5601 5153 5461 5371 4328 4243 4405 4068 3507 3548 3405 3002 2597 2725 2712 2106 1961 2002 1909 1487 1417 1536 1278 1012 1084 1058 904 709 736 738 545 501 536 472 397 337 357 316 252 267 271 202 195 179 183 140 124 136 106 74 91 89 65 54 61 55 60 60 45 33 31 24 39 28 23 30 31 14 20 14 16 22 12 6 10 21 6 9 8 6 4 6 11 7 9 5 2 4 2 3 6 3 2 0 2 2 2 1 1 2 1 1 4 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_2: [binsize: 128 max: 21143 count: 486326 average: 3852.66 | standard deviation: 2347.25 | 14072 1327 2443 4342 5729 5496 5083 5762 6663 7790 8820 8935 8050 8477 10578 11081 10605 10643 11287 11230 10992 12105 12745 10874 10606 11424 11647 10600 10427 10676 10079 9205 9306 10079 8868 7739 8487 8814 7465 6849 7339 7219 6182 6042 6453 5924 4980 5095 5515 4905 4170 4487 4307 3622 3327 3554 3511 2838 2751 2831 2713 2289 2261 2177 1939 1693 1757 1749 1388 1246 1314 1278 984 907 995 845 687 693 691 577 445 486 462 351 310 350 295 258 213 235 213 163 184 180 128 131 111 118 88 90 95 65 46 53 54 46 30 38 30 35 44 29 22 17 15 25 18 17 25 20 8 13 11 12 16 6 5 5 12 4 6 5 1 2 5 6 4 5 4 2 3 2 1 4 2 1 0 2 1 0 0 0 1 1 1 2 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_3: [binsize: 128 max: 21029 count: 262673 average: 3855.92 | standard deviation: 2346.94 | 7613 719 1281 2412 3057 2915 2705 2995 3515 4216 4658 4865 4345 4708 5775 5914 5831 5685 5999 6065 5900 6546 6925 5810 5685 6334 6402 5816 5538 5728 5445 4959 5125 5427 4721 4288 4566 4752 4113 3770 3950 3921 3354 3177 3570 3188 2747 2853 2894 2578 2161 2351 2394 1979 1826 1907 1860 1490 1492 1574 1355 1218 1287 1228 1063 904 968 963 718 715 688 631 503 510 541 433 325 391 367 327 264 250 276 194 191 186 177 139 124 122 103 89 83 91 74 64 68 65 52 34 41 41 28 38 35 19 24 23 25 25 16 16 11 14 9 14 10 6 5 11 6 7 3 4 6 6 1 5 9 2 3 3 5 2 1 5 3 4 1 0 1 0 2 2 1 1 0 0 1 2 1 1 1 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
|
|
All Non-Zero Cycle SW Prefetch Requests
|
|
------------------------------------
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Request vs. RubySystem State Profile
|
|
--------------------------------
|
|
|
|
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Message Delayed Cycles
|
|
----------------------
|
|
Total_delay_cycles: [binsize: 1 max: 34 count: 1498140 average: 0.00218137 | standard deviation: 0.184029 | 1497918 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ]
|
|
Total_nonPF_delay_cycles: [binsize: 1 max: 34 count: 1498140 average: 0.00218137 | standard deviation: 0.184029 | 1497918 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ]
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748999 average: 0 | standard deviation: 0 | 748999 ]
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 34 count: 749141 average: 0.00436233 | standard deviation: 0.260226 | 748919 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ]
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Resource Usage
|
|
--------------
|
|
page_size: 4096
|
|
user_time: 1568
|
|
system_time: 6
|
|
page_reclaims: 39818
|
|
page_faults: 0
|
|
swaps: 0
|
|
block_inputs: 0
|
|
block_outputs: 0
|
|
|
|
Network Stats
|
|
-------------
|
|
|
|
switch_0_inlinks: 2
|
|
switch_0_outlinks: 2
|
|
links_utilized_percent_switch_0: 0.0183566
|
|
links_utilized_percent_switch_0_link_0: 0.00734197 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_0_link_1: 0.0293713 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_0_Response_Data: 93592 748736 [ 0 93592 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Writeback_Control: 93607 748856 [ 0 0 93607 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Control: 93601 748808 [ 93601 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Data: 86982 695856 [ 86982 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Response_Data: 6638 53104 [ 0 6638 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_1_inlinks: 2
|
|
switch_1_outlinks: 2
|
|
links_utilized_percent_switch_1: 0.0183583
|
|
links_utilized_percent_switch_1_link_0: 0.0073431 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_1_link_1: 0.0293735 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_0_Response_Data: 93606 748848 [ 0 93606 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Writeback_Control: 93622 748976 [ 0 0 93622 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Control: 93610 748880 [ 93610 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Data: 86850 694800 [ 86850 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Response_Data: 6775 54200 [ 0 6775 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_2_inlinks: 2
|
|
switch_2_outlinks: 2
|
|
links_utilized_percent_switch_2: 0.0183623
|
|
links_utilized_percent_switch_2_link_0: 0.00734448 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_2_link_1: 0.0293801 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_0_Response_Data: 93626 749008 [ 0 93626 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Control: 93632 749056 [ 93632 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Data: 86768 694144 [ 86768 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Response_Data: 6877 55016 [ 0 6877 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_3_inlinks: 2
|
|
switch_3_outlinks: 2
|
|
links_utilized_percent_switch_3: 0.0183636
|
|
links_utilized_percent_switch_3_link_0: 0.00734471 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_3_link_1: 0.0293825 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_3_link_0_Response_Data: 93633 749064 [ 0 93633 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Writeback_Control: 93636 749088 [ 0 0 93636 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Control: 93645 749160 [ 93645 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Data: 86943 695544 [ 86943 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Response_Data: 6704 53632 [ 0 6704 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_4_inlinks: 2
|
|
switch_4_outlinks: 2
|
|
links_utilized_percent_switch_4: 0.0183624
|
|
links_utilized_percent_switch_4_link_0: 0.00734432 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_4_link_1: 0.0293806 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_4_link_0_Response_Data: 93622 748976 [ 0 93622 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Control: 93631 749048 [ 93631 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Data: 86839 694712 [ 86839 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Response_Data: 6810 54480 [ 0 6810 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_5_inlinks: 2
|
|
switch_5_outlinks: 2
|
|
links_utilized_percent_switch_5: 0.0183663
|
|
links_utilized_percent_switch_5_link_0: 0.00734561 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_5_link_1: 0.029387 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_5_link_0_Response_Data: 93632 749056 [ 0 93632 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_0_Writeback_Control: 93660 749280 [ 0 0 93660 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Control: 93647 749176 [ 93647 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Data: 87074 696592 [ 87074 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Response_Data: 6600 52800 [ 0 6600 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_6_inlinks: 2
|
|
switch_6_outlinks: 2
|
|
links_utilized_percent_switch_6: 0.0183699
|
|
links_utilized_percent_switch_6_link_0: 0.00734765 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_6_link_1: 0.0293922 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_6_link_0_Response_Data: 93657 749256 [ 0 93657 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_Writeback_Control: 93687 749496 [ 0 0 93687 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Control: 93662 749296 [ 93662 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Data: 86788 694304 [ 86788 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Response_Data: 6904 55232 [ 0 6904 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_7_inlinks: 2
|
|
switch_7_outlinks: 2
|
|
links_utilized_percent_switch_7: 0.018364
|
|
links_utilized_percent_switch_7_link_0: 0.00734538 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_7_link_1: 0.0293826 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_7_link_0_Response_Data: 93631 749048 [ 0 93631 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_Writeback_Control: 93655 749240 [ 0 0 93655 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Control: 93635 749080 [ 93635 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Data: 87012 696096 [ 87012 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Response_Data: 6646 53168 [ 0 6646 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_8_inlinks: 2
|
|
switch_8_outlinks: 2
|
|
links_utilized_percent_switch_8: 0.141605
|
|
links_utilized_percent_switch_8_link_0: 0.0566464 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_8_link_1: 0.226565 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_8_link_0_Control: 749063 5992504 [ 749063 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_0_Data: 695256 5562048 [ 695256 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Response_Data: 695045 5560360 [ 0 695045 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Writeback_Control: 749141 5993128 [ 0 0 749141 0 0 0 ] base_latency: 1
|
|
|
|
switch_9_inlinks: 2
|
|
switch_9_outlinks: 2
|
|
links_utilized_percent_switch_9: 0
|
|
links_utilized_percent_switch_9_link_0: 0 bw: 640000 base_latency: 1
|
|
links_utilized_percent_switch_9_link_1: 0 bw: 160000 base_latency: 1
|
|
|
|
|
|
switch_10_inlinks: 10
|
|
switch_10_outlinks: 10
|
|
links_utilized_percent_switch_10: 0.0461614
|
|
links_utilized_percent_switch_10_link_0: 0.0293679 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_1: 0.0293724 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_2: 0.0293779 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_3: 0.0293788 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_4: 0.0293773 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_5: 0.0293825 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_6: 0.0293906 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_7: 0.0293815 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_8: 0.226585 bw: 160000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1
|
|
|
|
outgoing_messages_switch_10_link_0_Response_Data: 93592 748736 [ 0 93592 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_0_Writeback_Control: 93607 748856 [ 0 0 93607 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Response_Data: 93606 748848 [ 0 93606 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Writeback_Control: 93622 748976 [ 0 0 93622 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_Response_Data: 93626 749008 [ 0 93626 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Response_Data: 93633 749064 [ 0 93633 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Writeback_Control: 93636 749088 [ 0 0 93636 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Response_Data: 93622 748976 [ 0 93622 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_Response_Data: 93632 749056 [ 0 93632 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_Writeback_Control: 93660 749280 [ 0 0 93660 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Response_Data: 93657 749256 [ 0 93657 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Writeback_Control: 93687 749496 [ 0 0 93687 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Response_Data: 93631 749048 [ 0 93631 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Writeback_Control: 93655 749240 [ 0 0 93655 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_8_Control: 749063 5992504 [ 749063 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_8_Data: 695256 5562048 [ 695256 0 0 0 0 0 ] base_latency: 1
|
|
|
|
l1u_0 cache stats:
|
|
l1u_0_total_misses: 93601
|
|
l1u_0_total_demand_misses: 93601
|
|
l1u_0_total_prefetches: 0
|
|
l1u_0_total_sw_prefetches: 0
|
|
l1u_0_total_hw_prefetches: 0
|
|
l1u_0_misses_per_transaction: inf
|
|
|
|
l1u_0_request_type_LD: 64.9138%
|
|
l1u_0_request_type_ST: 35.0862%
|
|
|
|
l1u_0_access_mode_type_SupervisorMode: 93601 100%
|
|
l1u_0_request_size: [binsize: log2 max: 1 count: 93601 average: 1 | standard deviation: 0 | 0 93601 ]
|
|
|
|
l1u_1 cache stats:
|
|
l1u_1_total_misses: 93610
|
|
l1u_1_total_demand_misses: 93610
|
|
l1u_1_total_prefetches: 0
|
|
l1u_1_total_sw_prefetches: 0
|
|
l1u_1_total_hw_prefetches: 0
|
|
l1u_1_misses_per_transaction: inf
|
|
|
|
l1u_1_request_type_LD: 64.9364%
|
|
l1u_1_request_type_ST: 35.0636%
|
|
|
|
l1u_1_access_mode_type_SupervisorMode: 93610 100%
|
|
l1u_1_request_size: [binsize: log2 max: 1 count: 93610 average: 1 | standard deviation: 0 | 0 93610 ]
|
|
|
|
l1u_2 cache stats:
|
|
l1u_2_total_misses: 93632
|
|
l1u_2_total_demand_misses: 93632
|
|
l1u_2_total_prefetches: 0
|
|
l1u_2_total_sw_prefetches: 0
|
|
l1u_2_total_hw_prefetches: 0
|
|
l1u_2_misses_per_transaction: inf
|
|
|
|
l1u_2_request_type_LD: 65.0301%
|
|
l1u_2_request_type_ST: 34.9699%
|
|
|
|
l1u_2_access_mode_type_SupervisorMode: 93632 100%
|
|
l1u_2_request_size: [binsize: log2 max: 1 count: 93632 average: 1 | standard deviation: 0 | 0 93632 ]
|
|
|
|
l1u_3 cache stats:
|
|
l1u_3_total_misses: 93645
|
|
l1u_3_total_demand_misses: 93645
|
|
l1u_3_total_prefetches: 0
|
|
l1u_3_total_sw_prefetches: 0
|
|
l1u_3_total_hw_prefetches: 0
|
|
l1u_3_misses_per_transaction: inf
|
|
|
|
l1u_3_request_type_LD: 64.768%
|
|
l1u_3_request_type_ST: 35.232%
|
|
|
|
l1u_3_access_mode_type_SupervisorMode: 93645 100%
|
|
l1u_3_request_size: [binsize: log2 max: 1 count: 93645 average: 1 | standard deviation: 0 | 0 93645 ]
|
|
|
|
l1u_4 cache stats:
|
|
l1u_4_total_misses: 93631
|
|
l1u_4_total_demand_misses: 93631
|
|
l1u_4_total_prefetches: 0
|
|
l1u_4_total_sw_prefetches: 0
|
|
l1u_4_total_hw_prefetches: 0
|
|
l1u_4_misses_per_transaction: inf
|
|
|
|
l1u_4_request_type_LD: 65.1579%
|
|
l1u_4_request_type_ST: 34.8421%
|
|
|
|
l1u_4_access_mode_type_SupervisorMode: 93631 100%
|
|
l1u_4_request_size: [binsize: log2 max: 1 count: 93631 average: 1 | standard deviation: 0 | 0 93631 ]
|
|
|
|
l1u_5 cache stats:
|
|
l1u_5_total_misses: 93647
|
|
l1u_5_total_demand_misses: 93647
|
|
l1u_5_total_prefetches: 0
|
|
l1u_5_total_sw_prefetches: 0
|
|
l1u_5_total_hw_prefetches: 0
|
|
l1u_5_misses_per_transaction: inf
|
|
|
|
l1u_5_request_type_LD: 64.9086%
|
|
l1u_5_request_type_ST: 35.0914%
|
|
|
|
l1u_5_access_mode_type_SupervisorMode: 93647 100%
|
|
l1u_5_request_size: [binsize: log2 max: 1 count: 93647 average: 1 | standard deviation: 0 | 0 93647 ]
|
|
|
|
l1u_6 cache stats:
|
|
l1u_6_total_misses: 93662
|
|
l1u_6_total_demand_misses: 93662
|
|
l1u_6_total_prefetches: 0
|
|
l1u_6_total_sw_prefetches: 0
|
|
l1u_6_total_hw_prefetches: 0
|
|
l1u_6_misses_per_transaction: inf
|
|
|
|
l1u_6_request_type_LD: 64.8353%
|
|
l1u_6_request_type_ST: 35.1647%
|
|
|
|
l1u_6_access_mode_type_SupervisorMode: 93662 100%
|
|
l1u_6_request_size: [binsize: log2 max: 1 count: 93662 average: 1 | standard deviation: 0 | 0 93662 ]
|
|
|
|
l1u_7 cache stats:
|
|
l1u_7_total_misses: 93635
|
|
l1u_7_total_demand_misses: 93635
|
|
l1u_7_total_prefetches: 0
|
|
l1u_7_total_sw_prefetches: 0
|
|
l1u_7_total_hw_prefetches: 0
|
|
l1u_7_misses_per_transaction: inf
|
|
|
|
l1u_7_request_type_LD: 64.8881%
|
|
l1u_7_request_type_ST: 35.1119%
|
|
|
|
l1u_7_access_mode_type_SupervisorMode: 93635 100%
|
|
l1u_7_request_size: [binsize: log2 max: 1 count: 93635 average: 1 | standard deviation: 0 | 0 93635 ]
|
|
|
|
--- DMA 0 ---
|
|
- Event Counts -
|
|
ReadRequest 0
|
|
WriteRequest 0
|
|
Data 0
|
|
Ack 0
|
|
|
|
- Transitions -
|
|
READY ReadRequest 0 <--
|
|
READY WriteRequest 0 <--
|
|
|
|
BUSY_RD Data 0 <--
|
|
|
|
BUSY_WR Ack 0 <--
|
|
|
|
--- Directory 0 ---
|
|
- Event Counts -
|
|
GETX 7426933
|
|
GETS 0
|
|
PUTX 694863
|
|
PUTX_NotOwner 393
|
|
DMA_READ 0
|
|
DMA_WRITE 0
|
|
Memory_Data 695045
|
|
Memory_Ack 694794
|
|
|
|
- Transitions -
|
|
I GETX 695106
|
|
I PUTX_NotOwner 0 <--
|
|
I DMA_READ 0 <--
|
|
I DMA_WRITE 0 <--
|
|
|
|
M GETX 53954
|
|
M PUTX 694863
|
|
M PUTX_NotOwner 393
|
|
M DMA_READ 0 <--
|
|
M DMA_WRITE 0 <--
|
|
|
|
M_DRD GETX 0 <--
|
|
M_DRD PUTX 0 <--
|
|
|
|
M_DWR GETX 0 <--
|
|
M_DWR PUTX 0 <--
|
|
|
|
M_DWRI Memory_Ack 0 <--
|
|
|
|
IM GETX 3188108
|
|
IM GETS 0 <--
|
|
IM PUTX 0 <--
|
|
IM PUTX_NotOwner 0 <--
|
|
IM DMA_READ 0 <--
|
|
IM DMA_WRITE 0 <--
|
|
IM Memory_Data 695045
|
|
|
|
MI GETX 3489765
|
|
MI GETS 0 <--
|
|
MI PUTX 0 <--
|
|
MI PUTX_NotOwner 0 <--
|
|
MI DMA_READ 0 <--
|
|
MI DMA_WRITE 0 <--
|
|
MI Memory_Ack 694794
|
|
|
|
ID GETX 0 <--
|
|
ID GETS 0 <--
|
|
ID PUTX 0 <--
|
|
ID PUTX_NotOwner 0 <--
|
|
ID DMA_READ 0 <--
|
|
ID DMA_WRITE 0 <--
|
|
ID Memory_Data 0 <--
|
|
|
|
ID_W GETX 0 <--
|
|
ID_W GETS 0 <--
|
|
ID_W PUTX 0 <--
|
|
ID_W PUTX_NotOwner 0 <--
|
|
ID_W DMA_READ 0 <--
|
|
ID_W DMA_WRITE 0 <--
|
|
ID_W Memory_Ack 0 <--
|
|
|
|
--- L1Cache 0 ---
|
|
- Event Counts -
|
|
Load 60760
|
|
Ifetch 0
|
|
Store 32841
|
|
Data 93592
|
|
Fwd_GETX 6638
|
|
Inv 0
|
|
Replacement 93569
|
|
Writeback_Ack 86918
|
|
Writeback_Nack 51
|
|
|
|
- Transitions -
|
|
I Load 60760
|
|
I Ifetch 0 <--
|
|
I Store 32841
|
|
I Inv 0 <--
|
|
I Replacement 6587
|
|
|
|
II Writeback_Nack 51
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6587
|
|
M Inv 0 <--
|
|
M Replacement 86982
|
|
|
|
MI Fwd_GETX 51
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86918
|
|
|
|
IS Data 60754
|
|
|
|
IM Data 32838
|
|
|
|
--- L1Cache 1 ---
|
|
- Event Counts -
|
|
Load 60787
|
|
Ifetch 0
|
|
Store 32823
|
|
Data 93606
|
|
Fwd_GETX 6775
|
|
Inv 0
|
|
Replacement 93578
|
|
Writeback_Ack 86801
|
|
Writeback_Nack 46
|
|
|
|
- Transitions -
|
|
I Load 60787
|
|
I Ifetch 0 <--
|
|
I Store 32823
|
|
I Inv 0 <--
|
|
I Replacement 6728
|
|
|
|
II Writeback_Nack 46
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6729
|
|
M Inv 0 <--
|
|
M Replacement 86850
|
|
|
|
MI Fwd_GETX 46
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86801
|
|
|
|
IS Data 60784
|
|
|
|
IM Data 32822
|
|
|
|
--- L1Cache 2 ---
|
|
- Event Counts -
|
|
Load 60889
|
|
Ifetch 0
|
|
Store 32743
|
|
Data 93626
|
|
Fwd_GETX 6877
|
|
Inv 0
|
|
Replacement 93600
|
|
Writeback_Ack 86717
|
|
Writeback_Nack 43
|
|
|
|
- Transitions -
|
|
I Load 60889
|
|
I Ifetch 0 <--
|
|
I Store 32743
|
|
I Inv 0 <--
|
|
I Replacement 6832
|
|
|
|
II Writeback_Nack 43
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6834
|
|
M Inv 0 <--
|
|
M Replacement 86768
|
|
|
|
MI Fwd_GETX 43
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86717
|
|
|
|
IS Data 60884
|
|
|
|
IM Data 32742
|
|
|
|
--- L1Cache 3 ---
|
|
- Event Counts -
|
|
Load 60652
|
|
Ifetch 0
|
|
Store 32993
|
|
Data 93633
|
|
Fwd_GETX 6704
|
|
Inv 0
|
|
Replacement 93613
|
|
Writeback_Ack 86899
|
|
Writeback_Nack 33
|
|
|
|
- Transitions -
|
|
I Load 60652
|
|
I Ifetch 0 <--
|
|
I Store 32993
|
|
I Inv 0 <--
|
|
I Replacement 6670
|
|
|
|
II Writeback_Nack 33
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6671
|
|
M Inv 0 <--
|
|
M Replacement 86943
|
|
|
|
MI Fwd_GETX 33
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86899
|
|
|
|
IS Data 60644
|
|
|
|
IM Data 32989
|
|
|
|
--- L1Cache 4 ---
|
|
- Event Counts -
|
|
Load 61008
|
|
Ifetch 0
|
|
Store 32623
|
|
Data 93622
|
|
Fwd_GETX 6810
|
|
Inv 0
|
|
Replacement 93599
|
|
Writeback_Ack 86779
|
|
Writeback_Nack 48
|
|
|
|
- Transitions -
|
|
I Load 61008
|
|
I Ifetch 0 <--
|
|
I Store 32623
|
|
I Inv 0 <--
|
|
I Replacement 6760
|
|
|
|
II Writeback_Nack 48
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6762
|
|
M Inv 0 <--
|
|
M Replacement 86839
|
|
|
|
MI Fwd_GETX 48
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86779
|
|
|
|
IS Data 61004
|
|
|
|
IM Data 32618
|
|
|
|
--- L1Cache 5 ---
|
|
- Event Counts -
|
|
Load 60785
|
|
Ifetch 0
|
|
Store 32862
|
|
Data 93632
|
|
Fwd_GETX 6600
|
|
Inv 0
|
|
Replacement 93615
|
|
Writeback_Ack 87003
|
|
Writeback_Nack 57
|
|
|
|
- Transitions -
|
|
I Load 60785
|
|
I Ifetch 0 <--
|
|
I Store 32862
|
|
I Inv 0 <--
|
|
I Replacement 6541
|
|
|
|
II Writeback_Nack 57
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6543
|
|
M Inv 0 <--
|
|
M Replacement 87074
|
|
|
|
MI Fwd_GETX 57
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 87003
|
|
|
|
IS Data 60776
|
|
|
|
IM Data 32856
|
|
|
|
--- L1Cache 6 ---
|
|
- Event Counts -
|
|
Load 60726
|
|
Ifetch 0
|
|
Store 32936
|
|
Data 93657
|
|
Fwd_GETX 6904
|
|
Inv 0
|
|
Replacement 93630
|
|
Writeback_Ack 86721
|
|
Writeback_Nack 62
|
|
|
|
- Transitions -
|
|
I Load 60726
|
|
I Ifetch 0 <--
|
|
I Store 32936
|
|
I Inv 0 <--
|
|
I Replacement 6842
|
|
|
|
II Writeback_Nack 62
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6842
|
|
M Inv 0 <--
|
|
M Replacement 86788
|
|
|
|
MI Fwd_GETX 62
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86721
|
|
|
|
IS Data 60724
|
|
|
|
IM Data 32933
|
|
|
|
--- L1Cache 7 ---
|
|
- Event Counts -
|
|
Load 60758
|
|
Ifetch 0
|
|
Store 32877
|
|
Data 93631
|
|
Fwd_GETX 6646
|
|
Inv 0
|
|
Replacement 93603
|
|
Writeback_Ack 86956
|
|
Writeback_Nack 53
|
|
|
|
- Transitions -
|
|
I Load 60758
|
|
I Ifetch 0 <--
|
|
I Store 32877
|
|
I Inv 0 <--
|
|
I Replacement 6591
|
|
|
|
II Writeback_Nack 53
|
|
|
|
M Load 0 <--
|
|
M Ifetch 0 <--
|
|
M Store 0 <--
|
|
M Fwd_GETX 6593
|
|
M Inv 0 <--
|
|
M Replacement 87012
|
|
|
|
MI Fwd_GETX 53
|
|
MI Inv 0 <--
|
|
MI Writeback_Ack 86956
|
|
|
|
IS Data 60756
|
|
|
|
IM Data 32875
|
|
|