Nilay Vaish 4333549575 cpu: o3: replace issueLatency with bool pipelined ... Currently, each op class has a parameter issueLat that denotes the cycles after which another op of the same class can be issued. As of now, this latency can either be one cycle (fully pipelined) or same as execution latency of the op (not at all pipelined). The fact that issueLat is a parameter of type Cycles makes one believe that it can be set to any value. To avoid the confusion, the parameter is being renamed as 'pipelined' with type boolean. If set to true, the op would execute in a fully pipelined fashion. Otherwise, it would execute in an unpipelined fashion.		2015-04-29 22:35:22 -05:00
..
Benchmarks.py	config: Specify OS type and release on command line	2015-03-19 04:06:14 -04:00
CacheConfig.py	config: Support full-system with SST's memory system	2015-04-08 15:56:06 -05:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	scons: Do not build the InOrderCPU	2015-01-20 08:12:45 -05:00
FSConfig.py	config: Support full-system with SST's memory system	2015-04-08 15:56:06 -05:00
MemConfig.py	config: Remove memory aliases and rely on class name	2015-04-20 12:46:29 -04:00
O3_ARM_v7a.py	cpu: o3: replace issueLatency with bool pipelined	2015-04-29 22:35:22 -05:00
Options.py	config: enable setting SE-mode environment variables from file	2015-04-23 13:40:18 -07:00
Simulation.py	config, cpu: fix progress interval for switched CPUs	2015-04-14 11:01:10 -05:00
SysPaths.py	config: expand '~' and '~user' in paths	2015-03-23 16:14:19 -07:00