562 lines
18 KiB
Text
562 lines
18 KiB
Text
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 1234
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randomization: 1
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cycle_period: 1
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block_size_bytes: 64
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block_size_bits: 6
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memory_size_bytes: 134217728
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memory_size_bits: 27
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology:
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virtual_net_0: active, ordered
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virtual_net_1: active, ordered
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virtual_net_2: active, unordered
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virtual_net_3: active, unordered
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virtual_net_4: active, unordered
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virtual_net_5: active, unordered
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virtual_net_6: inactive
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virtual_net_7: inactive
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virtual_net_8: inactive
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virtual_net_9: inactive
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Mar/18/2010 14:59:23
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 0.7
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Virtual_time_in_minutes: 0.0116667
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Virtual_time_in_hours: 0.000194444
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Virtual_time_in_days: 8.10185e-06
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Ruby_current_time: 222961
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Ruby_start_time: 0
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Ruby_cycles: 222961
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mbytes_resident: 30.5156
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mbytes_total: 203.461
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resident_ratio: 0.150021
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ruby_cycles_executed: [ 222962 ]
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Busy Controller Counts:
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L1Cache-0:0
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Directory-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 16 count: 998 average: 15.7946 | standard deviation: 1.13528 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 84 899 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 128 max: 23668 count: 983 average: 3530.64 | standard deviation: 5276.54 | 101 19 29 85 80 66 72 59 50 28 40 22 22 14 14 10 5 3 6 7 5 5 2 3 4 1 2 1 1 1 0 2 0 1 2 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 1 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 3 3 3 2 2 0 1 2 2 5 6 1 9 3 2 3 2 3 3 2 3 8 2 2 2 3 2 3 5 4 1 4 1 1 0 4 3 3 1 3 4 1 1 3 0 1 0 1 0 0 1 2 0 0 1 0 1 0 1 0 1 0 1 2 1 0 0 1 1 2 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_2: [binsize: 128 max: 19690 count: 100 average: 3024.87 | standard deviation: 5133.9 | 15 3 2 5 6 12 9 4 5 2 7 1 5 2 1 0 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ]
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miss_latency_3: [binsize: 128 max: 23668 count: 883 average: 3587.92 | standard deviation: 5292.25 | 86 16 27 80 74 54 63 55 45 26 33 21 17 12 13 10 3 3 5 7 5 4 2 3 4 1 2 1 1 1 0 2 0 1 1 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 0 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 2 2 3 2 2 0 1 2 2 5 6 1 9 3 2 1 2 3 3 2 3 6 1 2 2 3 1 3 5 4 1 4 1 1 0 3 2 3 1 3 3 1 1 2 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 8816
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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Network Stats
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-------------
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.13187
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links_utilized_percent_switch_0_link_0: 0.0481867 bw: 640000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.215553 bw: 160000 base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.123292
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links_utilized_percent_switch_1_link_0: 0.0538379 bw: 640000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.192747 bw: 160000 base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Data: 772 55584 [ 0 0 0 0 0 772 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 0.20415
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links_utilized_percent_switch_2_link_0: 0.192747 bw: 160000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 0.215553 bw: 160000 base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
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Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
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system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 889
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 889
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 9.67379%
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 90.3262%
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 889 100%
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system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 4 count: 889 average: 1.29021 | standard deviation: 0.887856 | 0 803 0 0 86 ]
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Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 860
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 860
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 9.76744%
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 90.2326%
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 860 100%
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system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 4 count: 860 average: 1.29302 | standard deviation: 0.89169 | 0 776 0 0 84 ]
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--- L1Cache 0 ---
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- Event Counts -
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Load 100
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Ifetch 0
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Store 887
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L2_Replacement 855
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L1_to_L2 318465
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L2_to_L1D 29
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L2_to_L1I 0
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Other_GETX 0
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Other_GETS 0
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Ack 0
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Shared_Ack 0
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Data 0
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Shared_Data 0
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Exclusive_Data 860
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Writeback_Ack 855
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Writeback_Nack 0
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All_acks 0
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All_acks_no_sharers 859
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- Transitions -
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I Load 84
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I Ifetch 0 <--
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I Store 776
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I L2_Replacement 0 <--
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I L1_to_L2 0 <--
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I L2_to_L1D 0 <--
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I L2_to_L1I 0 <--
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I Other_GETX 0 <--
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I Other_GETS 0 <--
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S Load 0 <--
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S Ifetch 0 <--
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S Store 0 <--
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S L2_Replacement 0 <--
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S L1_to_L2 0 <--
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S L2_to_L1D 0 <--
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S L2_to_L1I 0 <--
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S Other_GETX 0 <--
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S Other_GETS 0 <--
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O Load 0 <--
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O Ifetch 0 <--
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O Store 0 <--
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O L2_Replacement 0 <--
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O L1_to_L2 0 <--
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O L2_to_L1D 0 <--
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O L2_to_L1I 0 <--
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O Other_GETX 0 <--
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O Other_GETS 0 <--
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M Load 0 <--
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M Ifetch 0 <--
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M Store 1
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M L2_Replacement 82
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M L1_to_L2 82
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M L2_to_L1D 0 <--
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M L2_to_L1I 0 <--
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M Other_GETX 0 <--
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M Other_GETS 0 <--
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MM Load 16
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MM Ifetch 0 <--
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MM Store 102
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MM L2_Replacement 773
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MM L1_to_L2 804
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MM L2_to_L1D 29
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MM L2_to_L1I 0 <--
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MM Other_GETX 0 <--
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MM Other_GETS 0 <--
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IM Load 0 <--
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IM Ifetch 0 <--
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IM Store 0 <--
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IM L2_Replacement 0 <--
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IM L1_to_L2 276294
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IM Other_GETX 0 <--
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IM Other_GETS 0 <--
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IM Ack 0 <--
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IM Data 0 <--
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IM Exclusive_Data 776
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SM Load 0 <--
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SM Ifetch 0 <--
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SM Store 0 <--
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SM L2_Replacement 0 <--
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SM L1_to_L2 0 <--
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SM Other_GETX 0 <--
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SM Other_GETS 0 <--
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SM Ack 0 <--
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SM Data 0 <--
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OM Load 0 <--
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OM Ifetch 0 <--
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OM Store 0 <--
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OM L2_Replacement 0 <--
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OM L1_to_L2 0 <--
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OM Other_GETX 0 <--
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OM Other_GETS 0 <--
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OM Ack 0 <--
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OM All_acks 0 <--
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OM All_acks_no_sharers 0 <--
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ISM Load 0 <--
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ISM Ifetch 0 <--
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ISM Store 0 <--
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ISM L2_Replacement 0 <--
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ISM L1_to_L2 0 <--
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ISM Ack 0 <--
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ISM All_acks_no_sharers 0 <--
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M_W Load 0 <--
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M_W Ifetch 0 <--
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M_W Store 0 <--
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M_W L2_Replacement 0 <--
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M_W L1_to_L2 1192
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M_W Ack 0 <--
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M_W All_acks_no_sharers 83
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MM_W Load 0 <--
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MM_W Ifetch 0 <--
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MM_W Store 4
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MM_W L2_Replacement 0 <--
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MM_W L1_to_L2 11046
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MM_W Ack 0 <--
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MM_W All_acks_no_sharers 776
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IS Load 0 <--
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IS Ifetch 0 <--
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IS Store 0 <--
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IS L2_Replacement 0 <--
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IS L1_to_L2 29047
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IS Other_GETX 0 <--
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IS Other_GETS 0 <--
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IS Ack 0 <--
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IS Shared_Ack 0 <--
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IS Data 0 <--
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IS Shared_Data 0 <--
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IS Exclusive_Data 84
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SS Load 0 <--
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SS Ifetch 0 <--
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SS Store 0 <--
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SS L2_Replacement 0 <--
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SS L1_to_L2 0 <--
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SS Ack 0 <--
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SS Shared_Ack 0 <--
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SS All_acks 0 <--
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SS All_acks_no_sharers 0 <--
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OI Load 0 <--
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OI Ifetch 0 <--
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OI Store 0 <--
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OI L2_Replacement 0 <--
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OI L1_to_L2 0 <--
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OI Other_GETX 0 <--
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OI Other_GETS 0 <--
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OI Writeback_Ack 0 <--
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MI Load 0 <--
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MI Ifetch 0 <--
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MI Store 4
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MI L2_Replacement 0 <--
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MI L1_to_L2 0 <--
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MI Other_GETX 0 <--
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MI Other_GETS 0 <--
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MI Writeback_Ack 855
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II Load 0 <--
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II Ifetch 0 <--
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II Store 0 <--
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II L2_Replacement 0 <--
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II L1_to_L2 0 <--
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II Other_GETX 0 <--
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II Other_GETS 0 <--
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II Writeback_Ack 0 <--
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II Writeback_Nack 0 <--
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Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
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memory_total_requests: 1632
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memory_reads: 860
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memory_writes: 772
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memory_refreshes: 465
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memory_total_request_delays: 1106
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memory_delays_per_request: 0.677696
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memory_delays_in_input_queue: 152
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memory_delays_behind_head_of_bank_queue: 0
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memory_delays_stalled_at_head_of_bank_queue: 954
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memory_stalls_for_bank_busy: 245
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memory_stalls_for_random_busy: 0
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memory_stalls_for_anti_starvation: 0
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memory_stalls_for_arbitration: 77
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memory_stalls_for_bus: 374
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memory_stalls_for_tfaw: 0
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memory_stalls_for_read_write_turnaround: 150
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memory_stalls_for_read_read_turnaround: 108
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accesses_per_bank: 35 39 45 95 73 66 68 49 65 50 44 55 48 35 48 57 45 44 54 56 48 27 42 58 48 39 39 44 54 55 48 59
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--- Directory 0 ---
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- Event Counts -
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GETX 809
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GETS 84
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PUT 1454
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Unblock 858
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Writeback_Clean 0
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Writeback_Dirty 0
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Writeback_Exclusive_Clean 82
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Writeback_Exclusive_Dirty 772
|
|
DMA_READ 0
|
|
DMA_WRITE 0
|
|
Memory_Data 860
|
|
Memory_Ack 772
|
|
Ack 0
|
|
Shared_Ack 0
|
|
Shared_Data 0
|
|
Exclusive_Data 0
|
|
All_acks_and_data 0
|
|
All_acks_and_data_no_sharers 0
|
|
|
|
- Transitions -
|
|
NO GETX 0 <--
|
|
NO GETS 0 <--
|
|
NO PUT 855
|
|
NO DMA_READ 0 <--
|
|
NO DMA_WRITE 0 <--
|
|
|
|
O GETX 0 <--
|
|
O GETS 0 <--
|
|
O PUT 0 <--
|
|
O DMA_READ 0 <--
|
|
O DMA_WRITE 0 <--
|
|
|
|
E GETX 776
|
|
E GETS 84
|
|
E PUT 0 <--
|
|
E DMA_READ 0 <--
|
|
E DMA_WRITE 0 <--
|
|
|
|
NO_B GETX 0 <--
|
|
NO_B GETS 0 <--
|
|
NO_B PUT 599
|
|
NO_B Unblock 858
|
|
NO_B DMA_READ 0 <--
|
|
NO_B DMA_WRITE 0 <--
|
|
|
|
O_B GETX 0 <--
|
|
O_B GETS 0 <--
|
|
O_B PUT 0 <--
|
|
O_B Unblock 0 <--
|
|
O_B DMA_READ 0 <--
|
|
O_B DMA_WRITE 0 <--
|
|
|
|
NO_B_W GETX 0 <--
|
|
NO_B_W GETS 0 <--
|
|
NO_B_W PUT 0 <--
|
|
NO_B_W Unblock 0 <--
|
|
NO_B_W DMA_READ 0 <--
|
|
NO_B_W DMA_WRITE 0 <--
|
|
NO_B_W Memory_Data 860
|
|
|
|
O_B_W GETX 0 <--
|
|
O_B_W GETS 0 <--
|
|
O_B_W PUT 0 <--
|
|
O_B_W Unblock 0 <--
|
|
O_B_W DMA_READ 0 <--
|
|
O_B_W DMA_WRITE 0 <--
|
|
O_B_W Memory_Data 0 <--
|
|
|
|
NO_W GETX 0 <--
|
|
NO_W GETS 0 <--
|
|
NO_W PUT 0 <--
|
|
NO_W DMA_READ 0 <--
|
|
NO_W DMA_WRITE 0 <--
|
|
NO_W Memory_Data 0 <--
|
|
|
|
O_W GETX 0 <--
|
|
O_W GETS 0 <--
|
|
O_W PUT 0 <--
|
|
O_W DMA_READ 0 <--
|
|
O_W DMA_WRITE 0 <--
|
|
O_W Memory_Data 0 <--
|
|
|
|
NO_DW_B_W GETX 0 <--
|
|
NO_DW_B_W GETS 0 <--
|
|
NO_DW_B_W PUT 0 <--
|
|
NO_DW_B_W DMA_READ 0 <--
|
|
NO_DW_B_W DMA_WRITE 0 <--
|
|
NO_DW_B_W Ack 0 <--
|
|
NO_DW_B_W Exclusive_Data 0 <--
|
|
NO_DW_B_W All_acks_and_data_no_sharers 0 <--
|
|
|
|
NO_DR_B_W GETX 0 <--
|
|
NO_DR_B_W GETS 0 <--
|
|
NO_DR_B_W PUT 0 <--
|
|
NO_DR_B_W DMA_READ 0 <--
|
|
NO_DR_B_W DMA_WRITE 0 <--
|
|
NO_DR_B_W Memory_Data 0 <--
|
|
NO_DR_B_W Ack 0 <--
|
|
NO_DR_B_W Shared_Ack 0 <--
|
|
NO_DR_B_W Shared_Data 0 <--
|
|
NO_DR_B_W Exclusive_Data 0 <--
|
|
|
|
NO_DR_B_D GETX 0 <--
|
|
NO_DR_B_D GETS 0 <--
|
|
NO_DR_B_D PUT 0 <--
|
|
NO_DR_B_D DMA_READ 0 <--
|
|
NO_DR_B_D DMA_WRITE 0 <--
|
|
NO_DR_B_D Ack 0 <--
|
|
NO_DR_B_D Shared_Ack 0 <--
|
|
NO_DR_B_D Shared_Data 0 <--
|
|
NO_DR_B_D Exclusive_Data 0 <--
|
|
NO_DR_B_D All_acks_and_data 0 <--
|
|
NO_DR_B_D All_acks_and_data_no_sharers 0 <--
|
|
|
|
NO_DR_B GETX 0 <--
|
|
NO_DR_B GETS 0 <--
|
|
NO_DR_B PUT 0 <--
|
|
NO_DR_B DMA_READ 0 <--
|
|
NO_DR_B DMA_WRITE 0 <--
|
|
NO_DR_B Ack 0 <--
|
|
NO_DR_B Shared_Ack 0 <--
|
|
NO_DR_B Shared_Data 0 <--
|
|
NO_DR_B Exclusive_Data 0 <--
|
|
NO_DR_B All_acks_and_data 0 <--
|
|
NO_DR_B All_acks_and_data_no_sharers 0 <--
|
|
|
|
NO_DW_W GETX 0 <--
|
|
NO_DW_W GETS 0 <--
|
|
NO_DW_W PUT 0 <--
|
|
NO_DW_W DMA_READ 0 <--
|
|
NO_DW_W DMA_WRITE 0 <--
|
|
NO_DW_W Memory_Ack 0 <--
|
|
|
|
O_DR_B_W GETX 0 <--
|
|
O_DR_B_W GETS 0 <--
|
|
O_DR_B_W PUT 0 <--
|
|
O_DR_B_W DMA_READ 0 <--
|
|
O_DR_B_W DMA_WRITE 0 <--
|
|
O_DR_B_W Memory_Data 0 <--
|
|
|
|
O_DR_B GETX 0 <--
|
|
O_DR_B GETS 0 <--
|
|
O_DR_B PUT 0 <--
|
|
O_DR_B DMA_READ 0 <--
|
|
O_DR_B DMA_WRITE 0 <--
|
|
O_DR_B Ack 0 <--
|
|
O_DR_B All_acks_and_data_no_sharers 0 <--
|
|
|
|
WB GETX 0 <--
|
|
WB GETS 0 <--
|
|
WB PUT 0 <--
|
|
WB Unblock 0 <--
|
|
WB Writeback_Clean 0 <--
|
|
WB Writeback_Dirty 0 <--
|
|
WB Writeback_Exclusive_Clean 82
|
|
WB Writeback_Exclusive_Dirty 772
|
|
WB DMA_READ 0 <--
|
|
WB DMA_WRITE 0 <--
|
|
|
|
WB_O_W GETX 0 <--
|
|
WB_O_W GETS 0 <--
|
|
WB_O_W PUT 0 <--
|
|
WB_O_W DMA_READ 0 <--
|
|
WB_O_W DMA_WRITE 0 <--
|
|
WB_O_W Memory_Ack 0 <--
|
|
|
|
WB_E_W GETX 33
|
|
WB_E_W GETS 0 <--
|
|
WB_E_W PUT 0 <--
|
|
WB_E_W DMA_READ 0 <--
|
|
WB_E_W DMA_WRITE 0 <--
|
|
WB_E_W Memory_Ack 772
|
|
|