22c04190c6
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
506 lines
16 KiB
C++
506 lines
16 KiB
C++
/*
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* Copyright (c) 2011-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Dam Sunwoo
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* Matt Horsnell
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* Andreas Sandberg
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*/
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#ifndef __ARCH_ARM_PMU_HH__
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#define __ARCH_ARM_PMU_HH__
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#include <map>
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#include <memory>
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#include <vector>
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#include "arch/arm/isa_device.hh"
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#include "arch/arm/registers.hh"
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#include "sim/probe/probe.hh"
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#include "sim/sim_object.hh"
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class ArmPMUParams;
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class Platform;
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class ThreadContext;
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namespace ArmISA {
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/**
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* Model of an ARM PMU version 3
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*
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* This class implements a subset of the ARM PMU v3 specification as
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* described in the ARMv8 reference manual. It supports most of the
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* features of the PMU, however the following features are known to be
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* missing:
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*
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* <ul>
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* <li>Event filtering (e.g., from different privilege levels).
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* <li>Access controls (the PMU currently ignores the execution level).
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* <li>The chain counter (event no. 0x1E) is unimplemented.
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* </ul>
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*
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* The PMU itself does not implement any events, in merely provides an
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* interface for the configuration scripts to hook up probes that
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* drive events. Configuration scripts should call addEventProbe() to
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* configure custom events or high-level methods to configure
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* architected events. The Python implementation of addEventProbe()
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* automatically delays event type registration until after
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* instantiation.
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*
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* In order to support CPU switching and some combined counters (e.g.,
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* memory references synthesized from loads and stores), the PMU
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* allows multiple probes per event type. When creating a system that
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* switches between CPU models that share the same PMU, PMU events for
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* all of the CPU models can be registered with the PMU.
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*
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* @see The ARM Architecture Refererence Manual (DDI 0487A)
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*
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*/
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class PMU : public SimObject, public ArmISA::BaseISADevice {
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public:
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PMU(const ArmPMUParams *p);
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~PMU();
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void addEventProbe(unsigned int id, SimObject *obj, const char *name);
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public: // SimObject and related interfaces
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void drainResume() override;
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public: // ISA Device interface
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/**
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* Set a register within the PMU.
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*
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* @param misc_reg Register number (see miscregs.hh)
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* @param val Value to store
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*/
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void setMiscReg(int misc_reg, MiscReg val) override;
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/**
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* Read a register within the PMU.
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*
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* @param misc_reg Register number (see miscregs.hh)
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* @return Register value.
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*/
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MiscReg readMiscReg(int misc_reg) override;
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protected: // PMU register types and constants
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BitUnion32(PMCR_t)
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// PMU Enable
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Bitfield<0> e;
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// Event counter reset
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Bitfield<1> p;
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// Cycle counter reset
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Bitfield<2> c;
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// Cycle counter divider enable
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Bitfield<3> d;
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// Export enable
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Bitfield<4> x;
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// Disable PMCCNTR when event counting is prohibited
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Bitfield<5> dp;
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// Long Cycle counter enable
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Bitfield<6> lc;
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// Number of event counters implemented
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Bitfield<15, 11> n;
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// Implementation ID
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Bitfield<23, 16> idcode;
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// Implementer code
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Bitfield<31, 24> imp;
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EndBitUnion(PMCR_t)
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BitUnion32(PMSELR_t)
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// Performance counter selector
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Bitfield<4, 0> sel;
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EndBitUnion(PMSELR_t)
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BitUnion32(PMEVTYPER_t)
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Bitfield<9, 0> evtCount;
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// Secure EL3 filtering
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Bitfield<26> m;
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// Non-secure EL2 mode filtering
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Bitfield<27> nsh;
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// Non-secure EL0 mode filtering
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Bitfield<28> nsu;
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// Non-secure EL1 mode filtering
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Bitfield<29> nsk;
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// EL0 filtering
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Bitfield<30> u;
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// EL1 filtering
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Bitfield<31> p;
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EndBitUnion(PMEVTYPER_t)
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/**
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* Counter ID within the PMU.
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*
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* This value is typically used to index into various registers
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* controlling interrupts and overflows. The value normally in the
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* [0, 31] range, where 31 refers to the cycle counter.
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*/
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typedef unsigned int CounterId;
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/** Cycle Count Register Number */
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static const CounterId PMCCNTR = 31;
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/**
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* Event type ID.
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*
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* See the PMU documentation for a list of architected IDs.
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*/
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typedef unsigned int EventTypeId;
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/** ID of the software increment event */
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static const EventTypeId ARCH_EVENT_SW_INCR = 0x00;
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protected: /* High-level register and interrupt handling */
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MiscReg readMiscRegInt(int misc_reg);
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/**
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* PMCR write handling
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*
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* The PMCR register needs special handling since writing to it
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* changes PMU-global state (e.g., resets all counters).
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*
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* @param val New PMCR value
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*/
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void setControlReg(PMCR_t val);
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/**
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* Reset all event counters excluding the cycle counter to zero.
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*/
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void resetEventCounts();
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/**
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* Deliver a PMU interrupt to the GIC
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*/
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void raiseInterrupt();
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/**
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* Get the value of a performance counter.
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*
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* This method returns the value of a general purpose performance
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* counter or the fixed-function cycle counter. Non-existing
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* counters are treated as constant '0'.
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*
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* @return Value of the performance counter, 0 if the counter does
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* not exist.
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*/
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uint64_t getCounterValue(CounterId id) const {
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return isValidCounter(id) ? getCounter(id).value : 0;
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}
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/**
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* Set the value of a performance counter.
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*
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* This method sets the value of a general purpose performance
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* counter or the fixed-function cycle counter. Writes to
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* non-existing counters are ignored.
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*/
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void setCounterValue(CounterId id, uint64_t val);
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/**
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* Get the type and filter settings of a counter (PMEVTYPER)
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*
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* This method implements a read from a PMEVTYPER register. It
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* returns the type value and filter settings of a general purpose
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* performance counter or the cycle counter. Non-existing counters
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* are treated as constant '0'.
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*
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* @param id Counter ID within the PMU.
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* @return Performance counter type ID.
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*/
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PMEVTYPER_t getCounterTypeRegister(CounterId id) const;
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/**
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* Set the type and filter settings of a performance counter
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* (PMEVTYPER)
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*
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* This method implements a write to a PMEVTYPER register. It sets
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* the type value and filter settings of a general purpose
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* performance counter or the cycle counter. Writes to
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* non-existing counters are ignored. The method automatically
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* updates the probes used by the counter if it is enabled.
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*
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* @param id Counter ID within the PMU.
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* @param type Performance counter type and filter configuration..
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*/
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void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);
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protected: /* Probe handling and counter state */
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class ProbeListener : public ProbeListenerArgBase<uint64_t>
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{
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public:
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ProbeListener(PMU &_pmu, CounterId _id,
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ProbeManager *pm, const std::string &name)
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: ProbeListenerArgBase(pm, name),
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pmu(_pmu), id(_id) {}
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void notify(const uint64_t &val) override
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{
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pmu.handleEvent(id, val);
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}
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protected:
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PMU &pmu;
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const CounterId id;
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};
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typedef std::unique_ptr<ProbeListener> ProbeListenerUPtr;
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/**
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* Event type configuration
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*
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* The main purpose of this class is to describe how a PMU event
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* type is sampled. It is implemented as a probe factory that
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* returns a probe attached to the object the event is mointoring.
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*/
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struct EventType {
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/**
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* @param _obj Target SimObject
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* @param _name Probe name
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*/
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EventType(SimObject *_obj, const std::string &_name)
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: obj(_obj), name(_name) {}
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/**
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* Create and attach a probe used to drive this event.
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*
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* @param pmu PMU owning the probe.
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* @param CounterID counter ID within the PMU.
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* @return Pointer to a probe listener.
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*/
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std::unique_ptr<ProbeListener> create(PMU &pmu, CounterId cid) const
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{
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std::unique_ptr<ProbeListener> ptr;
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ptr.reset(new ProbeListener(pmu, cid,
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obj->getProbeManager(), name));
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return ptr;
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}
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/** SimObject being measured by this probe */
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SimObject *const obj;
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/** Probe name within obj */
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const std::string name;
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private:
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// Disable the default constructor
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EventType();
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};
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/** State of a counter within the PMU. */
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struct CounterState : public Serializable {
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CounterState()
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: eventId(0), filter(0), value(0), enabled(false),
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overflow64(false) {
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listeners.reserve(4);
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}
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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/**
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* Add an event count to the counter and check for overflow.
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*
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* @param delta Number of events to add to the counter.
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* @return true on overflow, false otherwise.
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*/
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bool add(uint64_t delta);
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public: /* Serializable state */
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/** Counter event ID */
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EventTypeId eventId;
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/** Filtering settings (evtCount is unused) */
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PMEVTYPER_t filter;
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/** Current value of the counter */
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uint64_t value;
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/** Is the counter enabled? */
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bool enabled;
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/** Is this a 64-bit counter? */
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bool overflow64;
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public: /* Configuration */
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/** Probe listeners driving this counter */
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std::vector<ProbeListenerUPtr> listeners;
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};
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/**
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* Handle an counting event triggered by a probe.
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*
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* This method is called by the ProbeListener class whenever an
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* active probe is triggered. Ths method adds the event count from
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* the probe to the affected counter, checks for overflows, and
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* delivers an interrupt if needed.
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*
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* @param id Counter ID affected by the probe.
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* @param delta Counter increment
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*/
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void handleEvent(CounterId id, uint64_t delta);
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/**
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* Is this a valid counter ID?
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*
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* @param id ID of counter within the PMU.
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*
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* @return true if counter is within the allowed range or the
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* cycle counter, false otherwise.
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*/
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bool isValidCounter(CounterId id) const {
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return id < counters.size() || id == PMCCNTR;
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}
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/**
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* Return the state of a counter.
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*
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* @param id ID of counter within the PMU.
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* @return Reference to a CounterState instance representing the
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* counter.
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*/
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CounterState &getCounter(CounterId id) {
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assert(isValidCounter(id));
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return id == PMCCNTR ? cycleCounter : counters[id];
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}
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/**
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* Return the state of a counter.
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*
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* @param id ID of counter within the PMU.
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* @return Reference to a CounterState instance representing the
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* counter.
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*/
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const CounterState &getCounter(CounterId id) const {
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assert(isValidCounter(id));
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return id == PMCCNTR ? cycleCounter : counters[id];
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}
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/**
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* Depending on counter configuration, add or remove the probes
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* driving the counter.
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*
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* Look at the state of a counter and (re-)attach the probes
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* needed to drive a counter if it is currently active. All probes
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* for the counter are detached if the counter is inactive.
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*
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* @param id ID of counter within the PMU.
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* @param ctr Reference to the counter's state
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*/
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void updateCounter(CounterId id, CounterState &ctr);
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/**
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* Check if a counter's settings allow it to be counted.
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*
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* @param ctr Counter state instance representing this counter.
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* @return false if the counter is active, true otherwise.
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*/
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bool isFiltered(const CounterState &ctr) const;
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/**
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* Call updateCounter() for each counter in the PMU if the
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* counter's state has changed..
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*
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* @see updateCounter()
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*/
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void updateAllCounters();
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protected: /* State that needs to be serialized */
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/** Performance Monitor Count Enable Register */
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MiscReg reg_pmcnten;
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/** Performance Monitor Control Register */
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PMCR_t reg_pmcr;
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/** Performance Monitor Selection Register */
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PMSELR_t reg_pmselr;
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/** Performance Monitor Interrupt Enable Register */
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MiscReg reg_pminten;
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/** Performance Monitor Overflow Status Register */
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MiscReg reg_pmovsr;
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/**
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* Performance counter ID register
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*
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* This register contains a bitmask of available architected
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* counters.
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*/
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uint64_t reg_pmceid;
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/** Remainder part when the clock counter is divided by 64 */
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unsigned clock_remainder;
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/** State of all general-purpose counters supported by PMU */
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std::vector<CounterState> counters;
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/** State of the cycle counter */
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CounterState cycleCounter;
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protected: /* Configuration and constants */
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/** Constant (configuration-dependent) part of the PMCR */
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PMCR_t reg_pmcr_conf;
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/** PMCR write mask when accessed from the guest */
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static const MiscReg reg_pmcr_wr_mask;
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/** Performance monitor interrupt number */
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const unsigned int pmuInterrupt;
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/** Platform this device belongs to */
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Platform *const platform;
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/**
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* Event types supported by this PMU.
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*
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* Each event type ID can map to multiple EventType structures,
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* which enables the PMU to use multiple probes for a single
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* event. This can be useful in the following cases:
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* <ul>
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* <li>Some events can are increment by multiple different probe
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* points (e.g., the CPU memory access counter gets
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* incremented for both loads and stores).
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*
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* <li>A system switching between multiple CPU models can
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* register events for all models that will execute a thread
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* and tehreby ensure that the PMU continues to work.
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* </ul>
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*/
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std::multimap<EventTypeId, EventType> pmuEventTypes;
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};
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} // namespace ArmISA
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#endif
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