d2b57a7473
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
724 lines
82 KiB
Text
724 lines
82 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.737495 # Number of seconds simulated
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sim_ticks 737494828500 # Number of ticks simulated
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final_tick 737494828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 117861 # Simulator instruction rate (inst/s)
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host_op_rate 160511 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 62787760 # Simulator tick rate (ticks/s)
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host_mem_usage 243784 # Number of bytes of host memory used
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host_seconds 11745.84 # Real time elapsed on the host
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sim_insts 1384378545 # Number of instructions simulated
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sim_ops 1885333297 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 209536 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 94516480 # Number of bytes read from this memory
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system.physmem.bytes_read::total 94726016 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 209536 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 209536 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3274 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1476820 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1480094 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 284119 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 128158838 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 128442956 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 284119 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 284119 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 5736089 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 5736089 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 5736089 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 284119 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 128158838 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 134179045 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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system.cpu.numCycles 1474989658 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 524417855 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 399374260 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 35885746 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 373085909 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 286974367 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 58521049 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2814397 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 448543327 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2629766387 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 524417855 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 345495416 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 712413372 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 224871613 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 101150257 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2305 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 27764 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 417868916 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 11061583 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1445533834 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.549178 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.166303 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 733184926 50.72% 50.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 55708468 3.85% 54.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 112020823 7.75% 62.32% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 70937824 4.91% 67.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 82697525 5.72% 72.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 53946539 3.73% 76.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 34097920 2.36% 79.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 36269848 2.51% 81.55% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 266669961 18.45% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1445533834 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.355540 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.782905 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 495848393 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 80424598 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 675057973 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 10827570 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 183375300 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 81502199 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 23236 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3555990026 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 53741 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 183375300 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 535002639 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 31838463 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 561864 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 645033334 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 49722234 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3433849661 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 4442600 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 40377333 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 1619 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 3343633011 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 16242490520 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 15601606149 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 640884371 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1993152818 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 1350480193 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 55128 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 50419 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 136573484 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 1056851261 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 578467186 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 33770671 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 40675012 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 3200649154 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 58384 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2726502260 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 25388775 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 1314914344 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 3030342592 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 35409 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1445533834 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.886156 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.918040 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 525278081 36.34% 36.34% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 201262430 13.92% 50.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 215918123 14.94% 65.20% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 180162301 12.46% 77.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 154926049 10.72% 88.38% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 101550700 7.03% 95.40% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 47554041 3.29% 98.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 10922133 0.76% 99.45% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 7959976 0.55% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 1445533834 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 1492509 1.56% 1.56% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 23896 0.02% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 56884483 59.48% 61.06% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 37239793 38.94% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1265251443 46.41% 46.41% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 11240550 0.41% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.82% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.87% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.87% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 6876520 0.25% 47.12% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 5507594 0.20% 47.32% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 50 0.00% 47.32% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 23397304 0.86% 48.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 900321510 33.02% 81.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 512531999 18.80% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2726502260 # Type of FU issued
|
|
system.cpu.iq.rate 1.848489 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 95640681 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.035078 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 6886689526 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 4415187143 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2498660773 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 132878284 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 100500200 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 59720745 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2753616267 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 68526674 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 71560936 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 425462489 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 295662 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1252623 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 301470298 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 183375300 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 17460814 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1976242 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 3200787719 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 6982578 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 1056851261 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 578467186 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 47271 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 1974574 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 647 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 1252623 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 36804150 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 9241017 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 46045167 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2625801566 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 846122172 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 100700694 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 80181 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 1330053445 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 359055744 # Number of branches executed
|
|
system.cpu.iew.exec_stores 483931273 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.780217 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2586917302 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2558381518 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1475385900 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2766219416 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.734508 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.533358 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 1315443833 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 22975 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 41404056 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1262158536 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.493746 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.206193 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 581725846 46.09% 46.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 316852279 25.10% 71.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 102044776 8.08% 79.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 79824424 6.32% 85.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 53115957 4.21% 89.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 24396464 1.93% 91.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 17091653 1.35% 93.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 8923952 0.71% 93.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 78183185 6.19% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1262158536 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1384389561 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1885344313 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 908385660 # Number of memory references committed
|
|
system.cpu.commit.loads 631388772 # Number of loads committed
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
|
system.cpu.commit.branches 291350135 # Number of branches committed
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1653705231 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 78183185 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 4384745152 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6584968170 # The number of ROB writes
|
|
system.cpu.timesIdled 1343543 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 29455824 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1384378545 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1885333297 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1384378545 # Number of Instructions Simulated
|
|
system.cpu.cpi 1.065453 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.065453 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.938568 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.938568 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 12950426831 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2427369394 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 71525918 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 50683175 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 4109052133 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 13776084 # number of misc regfile writes
|
|
system.cpu.icache.replacements 27555 # number of replacements
|
|
system.cpu.icache.tagsinuse 1659.051734 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 417829104 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 29252 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 14283.779024 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1659.051734 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.810084 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.810084 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 417833790 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 417833790 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 417833790 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 417833790 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 417833790 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 417833790 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 35126 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 35126 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 35126 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 35126 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 35126 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 35126 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 348458500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 348458500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 348458500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 348458500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 348458500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 348458500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 417868916 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 417868916 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 417868916 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 417868916 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 417868916 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 417868916 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9920.244264 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 9920.244264 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 9920.244264 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 9920.244264 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 940 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 940 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 940 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 940 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 940 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 940 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34186 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 34186 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 34186 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 34186 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 34186 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 34186 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218551000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 218551000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218551000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 218551000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218551000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 218551000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6392.997133 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6392.997133 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1533020 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.909429 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1033013851 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1537116 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 672.046775 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.909429 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 756858216 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 756858216 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 276115103 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 276115103 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11921 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 11921 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11576 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 11576 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1032973319 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1032973319 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1032973319 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1032973319 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2483728 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2483728 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 820575 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 820575 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3304303 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3304303 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3304303 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3304303 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 90046240500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 90046240500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963890000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 33963890000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 124010130500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 124010130500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 124010130500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 124010130500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 759341944 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 759341944 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11925 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 11925 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11576 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11576 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1036277622 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1036277622 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1036277622 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1036277622 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003271 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003271 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000335 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000335 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.003189 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.003189 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.003189 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.003189 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36254.469290 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 36254.469290 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41390.354325 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41390.354325 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37529.890721 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37529.890721 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 108316 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 108316 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1019154 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1019154 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743098 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 743098 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1762252 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1762252 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1762252 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1762252 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464574 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1464574 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77477 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 77477 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1542051 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1542051 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1542051 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1542051 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50338229502 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 50338229502 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525857500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525857500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52864087002 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 52864087002 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52864087002 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 52864087002 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001929 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001929 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34370.560656 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34370.560656 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32601.384927 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32601.384927 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 1480259 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 32698.440647 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 88180 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.058281 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 3112.320696 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 61.394609 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 29524.725342 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.094980 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001874 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.901023 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.997877 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 25967 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 53813 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 79780 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 108316 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 108316 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6462 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 6462 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 25967 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 60275 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 86242 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 25967 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 60275 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 86242 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3285 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1410760 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1414045 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4932 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 4932 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66081 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66081 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3285 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1476841 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1480126 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3285 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1476841 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1480126 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 116334500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48797101500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 48913436000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2274840000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2274840000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 116334500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 51071941500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 51188276000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 116334500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 51071941500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 51188276000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 29252 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464573 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1493825 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 108316 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 108316 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4935 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 4935 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72543 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 72543 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 29252 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1537116 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1566368 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 29252 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1537116 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1566368 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.112300 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.963257 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.946593 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999392 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999392 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910922 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910922 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.112300 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.960787 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.944941 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.112300 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.960787 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.944941 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35413.850837 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34589.229564 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34591.145261 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.023834 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.023834 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35413.850837 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34581.882207 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 34583.728683 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35413.850837 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34581.882207 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 34583.728683 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3274 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410739 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1414013 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4932 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4932 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66081 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66081 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3274 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1476820 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1480094 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3274 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1476820 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1480094 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105728000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44228314000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44334042000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152892000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152892000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049197000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049197000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105728000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46277511000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 46383239000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105728000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46277511000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 46383239000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963243 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946572 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999392 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999392 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910922 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910922 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.944921 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.944921 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32293.219304 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.167012 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.348237 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.381199 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.381199 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|