1651 lines
188 KiB
Plaintext
1651 lines
188 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000261 # Number of seconds simulated
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sim_ticks 260712500 # Number of ticks simulated
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final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1018019 # Simulator instruction rate (inst/s)
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host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 401917302 # Simulator tick rate (ticks/s)
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host_mem_usage 306320 # Number of bytes of host memory used
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host_seconds 0.65 # Real time elapsed on the host
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sim_insts 660333 # Number of instructions simulated
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sim_ops 660333 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 521425 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 157788 # Number of instructions committed
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system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu0.num_func_calls 390 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 108684 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
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system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu0.num_mem_refs 73628 # number of memory refs
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system.cpu0.num_load_insts 48745 # Number of load instructions
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system.cpu0.num_store_insts 24883 # Number of store instructions
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system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
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system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles
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system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
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system.cpu0.Branches 26766 # Number of branches fetched
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system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction
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system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction
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system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction
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system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction
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system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu0.op_class::total 157850 # Class of executed instruction
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system.cpu0.dcache.tags.replacements 2 # number of replacements
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system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use
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system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks.
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system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
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system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
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system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses
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system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses
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system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits
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system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
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system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
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system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits
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system.cpu0.dcache.overall_hits::total 73215 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
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system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
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system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
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system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses
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system.cpu0.dcache.overall_misses::total 352 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses
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system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
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system.cpu0.dcache.writebacks::total 1 # number of writebacks
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system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
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|
system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
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|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
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|
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
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system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses
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|
system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses
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|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles
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|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles
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|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles
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|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles
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|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles
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|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles
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|
system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses
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|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 215 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 157384 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 467 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.numCycles 521425 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 168182 # Number of instructions committed
|
|
system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 110851 # number of integer instructions
|
|
system.cpu1.num_fp_insts 0 # number of float instructions
|
|
system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 54346 # number of memory refs
|
|
system.cpu1.num_load_insts 41092 # Number of load instructions
|
|
system.cpu1.num_store_insts 13254 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles
|
|
system.cpu1.Branches 34327 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 168214 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 53996 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 271 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4344000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003967 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003967 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008192 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008192 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.004994 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.004994 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.631902 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15119.631902 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17402.777778 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17402.777778 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3437.500000 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3437.500000 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 280 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 167849 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.numCycles 521424 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 165155 # Number of instructions committed
|
|
system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 110249 # number of integer instructions
|
|
system.cpu2.num_fp_insts 0 # number of float instructions
|
|
system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 54956 # number of memory refs
|
|
system.cpu2.num_load_insts 40791 # Number of load instructions
|
|
system.cpu2.num_store_insts 14165 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles
|
|
system.cpu2.Branches 33115 # Number of branches fetched
|
|
system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction
|
|
system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction
|
|
system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction
|
|
system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu2.op_class::total 165187 # Class of executed instruction
|
|
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses
|
|
system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 54608 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 269 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 269 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2653500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2653500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1938000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1938000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4591500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 4591500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4591500 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 4591500 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003948 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003948 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007663 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007663 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004902 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004902 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.tags.replacements 280 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 70.166597 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 164822 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 450.333333 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu2.icache.tags.tag_accesses 165554 # Number of tag accesses
|
|
system.cpu2.icache.tags.data_accesses 165554 # Number of data accesses
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 164822 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 164822 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 164822 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 164822 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 164822 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 164822 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.numCycles 521424 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 169208 # Number of instructions committed
|
|
system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 110441 # number of integer instructions
|
|
system.cpu3.num_fp_insts 0 # number of float instructions
|
|
system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 53219 # number of memory refs
|
|
system.cpu3.num_load_insts 40883 # Number of load instructions
|
|
system.cpu3.num_store_insts 12336 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles
|
|
system.cpu3.Branches 35047 # Number of branches fetched
|
|
system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction
|
|
system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction
|
|
system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction
|
|
system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu3.op_class::total 169240 # Class of executed instruction
|
|
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
|
|
system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses
|
|
system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 52867 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 270 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.tags.replacements 281 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
|
|
system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses
|
|
system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 168874 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 367 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002169 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.002169 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002169 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.002169 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002169 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.002169 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14636.239782 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 14636.239782 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 14636.239782 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 14636.239782 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5004500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5004500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5004500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 5004500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5004500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 5004500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002169 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.002169 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.002169 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13636.239782 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 349.411371 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 4 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 0.890694 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 231.985944 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 54.243981 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 6.369557 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 0.864661 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 47.217011 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 6.137141 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 0.888283 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 0.814098 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.003540 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.005332 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 19669 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 19669 # Number of data accesses
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 302 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 3 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
|
system.l2c.overall_hits::total 1220 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 372 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 592 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 64 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 23 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 16 # number of overall misses
|
|
system.l2c.overall_misses::total 592 # number of overall misses
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 795500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7472000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14963500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3340500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 446500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 19490500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3.data 104500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 4093500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 14963500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 740000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 840000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 3340500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1214500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 446500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 848500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 31056000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 14963500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 740000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 840000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 3340500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1214500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 446500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 848500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 31056000 # number of overall miss cycles
|
|
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.237548 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.174863 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53033.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 52619.718310 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52503.508772 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52195.312500 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 49611.111111 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 52393.817204 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52375 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52250 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52503.508772 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 52459.459459 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52503.508772 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 52459.459459 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 10 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 8 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 14 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 54 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 1 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 7 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 16 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 54 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 22 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 16 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 54 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 22 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1222000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 700497 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 700497 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 698998 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 3321992 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 645500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 604000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 6052000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 12113500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 600000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2295500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 42500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 15051500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 2805000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 85000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 297500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 42500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 3230000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 12113500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 7012500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 600000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 680000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 2295500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 943000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 42500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 646500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 24333500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 12113500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 7012500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 600000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 680000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 2295500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 943000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 42500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 646500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 24333500 # number of overall MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.181818 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.636364 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 43642.857143 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 43781.062500 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 43781.062500 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43687.375000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43710.421053 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43033.333333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 42619.718310 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42518.361582 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadResp 430 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 271 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 261 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 913 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 913 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1034 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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