798 lines
91 KiB
Text
798 lines
91 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000009 # Number of seconds simulated
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sim_ticks 9059000 # Number of ticks simulated
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final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 28083 # Simulator instruction rate (inst/s)
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host_op_rate 28078 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 106544733 # Simulator tick rate (ticks/s)
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host_mem_usage 213348 # Number of bytes of host memory used
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host_seconds 0.09 # Real time elapsed on the host
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sim_insts 2387 # Number of instructions simulated
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sim_ops 2387 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
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system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 272 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 17408 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 8990500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 272 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 1180771 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests
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system.physmem.totBusLat 1088000 # Total cycles spent in databus access
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system.physmem.totBankLat 4662000 # Total cycles spent in bank access
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system.physmem.avgQLat 4341.07 # Average queueing delay per request
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system.physmem.avgBankLat 17139.71 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 25480.78 # Average memory access latency
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system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 12.01 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.77 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 228 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 33053.31 # Average gap between requests
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 717 # DTB read hits
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system.cpu.dtb.read_misses 25 # DTB read misses
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system.cpu.dtb.read_acv 1 # DTB read access violations
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system.cpu.dtb.read_accesses 742 # DTB read accesses
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system.cpu.dtb.write_hits 359 # DTB write hits
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system.cpu.dtb.write_misses 19 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 378 # DTB write accesses
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system.cpu.dtb.data_hits 1076 # DTB hits
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system.cpu.dtb.data_misses 44 # DTB misses
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system.cpu.dtb.data_acv 1 # DTB access violations
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system.cpu.dtb.data_accesses 1120 # DTB accesses
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system.cpu.itb.fetch_hits 1063 # ITB hits
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system.cpu.itb.fetch_misses 30 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 1093 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 18119 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 1180 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 594 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 261 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 806 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 235 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 227 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 1168 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 1075 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 4086 # Type of FU issued
|
|
system.cpu.iq.rate 0.225509 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 344 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 1121 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 656 # Number of branches executed
|
|
system.cpu.iew.exec_stores 378 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.214526 # Inst execution rate
|
|
system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 3691 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1735 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2218 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 709 # Number of memory references committed
|
|
system.cpu.commit.loads 415 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 396 # Number of branches committed
|
|
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 11910 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 11291 # The number of ROB writes
|
|
system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
|
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 4685 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2864 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 813 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 813 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 250 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1063 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1063 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235183 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.235183 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.235183 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.235183 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.235183 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.235183 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47823.996000 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 47823.996000 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 47823.996000 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 47823.996000 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9236999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 9236999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9236999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 9236999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9236999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 9236999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175917 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.175917 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.175917 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49395.716578 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49395.716578 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 121.901566 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 93.245260 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 28.656305 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.003720 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9049000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3265500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 12314500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1324000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1324000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 9049000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 4589500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 13638500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 9049000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 4589500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 13638500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48390.374332 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53532.786885 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49655.241935 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55166.666667 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55166.666667 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 50141.544118 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 50141.544118 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6701279 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2512062 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9213341 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1027024 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1027024 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6701279 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3539086 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10240365 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6701279 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3539086 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10240365 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35835.716578 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41181.344262 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37150.568548 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 45.425217 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 774 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 45.425217 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.011090 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.011090 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 774 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 192 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 192 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 192 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 192 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5152500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5152500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4115500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 9268000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 9268000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 9268000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 9268000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 672 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 672 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 966 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 966 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 966 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 966 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165179 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.165179 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 50808.641975 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 48270.833333 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 48270.833333 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|