ab2f864af2
This patch includes the necessary regression updates to test the new ruby configuration system. The patch includes support for multiple ruby protocols and adds the ruby random tester. The patch removes atomic mode test for ruby since ruby does not support atomic mode acceses. These tests can be added back in when ruby supports atomic mode for real. --HG-- rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
51 lines
4.5 KiB
Plaintext
51 lines
4.5 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 14317 # Simulator instruction rate (inst/s)
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host_mem_usage 214996 # Number of bytes of host memory used
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host_seconds 0.18 # Real time elapsed on the host
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host_tick_rate 477706 # Simulator tick rate (ticks/s)
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sim_freq 1000000000 # Frequency of simulated ticks
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sim_insts 2577 # Number of instructions simulated
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sim_seconds 0.000086 # Number of seconds simulated
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sim_ticks 85988 # Number of ticks simulated
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system.cpu.dtb.data_accesses 717 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 709 # DTB hits
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system.cpu.dtb.data_misses 8 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 2597 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 2586 # ITB hits
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system.cpu.itb.fetch_misses 11 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 85988 # number of cpu cycles simulated
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system.cpu.num_insts 2577 # Number of instructions executed
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system.cpu.num_refs 717 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
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---------- End Simulation Statistics ----------
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