208 lines
8.2 KiB
Python
208 lines
8.2 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L1Cache(RubyCache):
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latency = 2
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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latency = 10
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#
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# Probe filter is a cache, latency is not used
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#
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class ProbeFilter(RubyCache):
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latency = 1
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def define_options(parser):
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parser.add_option("--allow-atomic-migration", action="store_true",
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help="allow migratory sharing for atomic only accessed blocks")
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parser.add_option("--pf-on", action="store_true",
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help="Hammer: enable Probe Filter")
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parser.add_option("--dir-on", action="store_true",
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help="Hammer: enable Full-bit Directory")
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def create_system(options, system, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MOESI_hammer':
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panic("This script requires the MOESI_hammer protocol to be built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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block_size_bits = int(math.log(options.cacheline_size, 2))
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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#
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l1i_cache = L1Cache(size = options.l1i_size,
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assoc = options.l1i_assoc,
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start_index_bit = block_size_bits)
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l1d_cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc,
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start_index_bit = block_size_bits)
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc,
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start_index_bit = block_size_bits)
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cpu_seq = RubySequencer(version = i,
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icache = l1i_cache,
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dcache = l1d_cache,
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physMemPort = system.physmem.port,
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physmem = system.physmem)
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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L2cacheMemory = l2_cache,
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no_mig_atomic = not \
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options.allow_atomic_migration)
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if options.recycle_latency:
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l1_cntrl.recycle_latency = options.recycle_latency
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exec("system.l1_cntrl%d = l1_cntrl" % i)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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phys_mem_size = long(system.physmem.range.second) - \
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long(system.physmem.range.first) + 1
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mem_module_size = phys_mem_size / options.num_dirs
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#
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# determine size and index bits for probe filter
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# By default, the probe filter size is configured to be twice the
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# size of the L2 cache.
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#
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pf_size = MemorySize(options.l2_size)
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pf_size.value = pf_size.value * 2
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dir_bits = int(math.log(options.num_dirs, 2))
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pf_bits = int(math.log(pf_size.value, 2))
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if options.numa_high_bit:
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if options.numa_high_bit > 0:
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# if numa high bit explicitly set, make sure it does not overlap
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# with the probe filter index
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assert(options.numa_high_bit - dir_bits > pf_bits)
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# set the probe filter start bit to just above the block offset
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pf_start_bit = 6
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else:
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if dir_bits > 0:
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pf_start_bit = dir_bits + 5
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else:
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pf_start_bit = 6
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(version = i)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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pf = ProbeFilter(size = pf_size, assoc = 4,
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start_index_bit = pf_start_bit)
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory( \
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version = i,
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size = dir_size,
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use_map = options.use_map,
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map_levels = \
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options.map_levels,
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numa_high_bit = \
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options.numa_high_bit),
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probeFilter = pf,
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memBuffer = mem_cntrl,
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probe_filter_enabled = options.pf_on,
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full_bit_dir_enabled = options.dir_on)
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if options.recycle_latency:
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dir_cntrl.recycle_latency = options.recycle_latency
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exec("system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_device in enumerate(dma_devices):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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physMemPort = system.physmem.port,
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physmem = system.physmem)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
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else:
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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if options.recycle_latency:
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dma_cntrl.recycle_latency = options.recycle_latency
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
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return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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