a91ee5abc2
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa. Now it's back to just debugging execution of code for the release (those unaligned memory access instruction pairs are still quite the pain i might add) arch/mips/isa_traits.hh: declare functions for .cc file arch/mips/isa_traits.cc: delete unnecessary overloaded functions implement condition code functions implement round function arch/mips/isa/base.isa: remove R31 constant... define in the operands.isa file instead arch/mips/isa/decoder.isa: wholesale changes once again to FP. Now the FP Condition Codes are implemented and the FP programs can run and complete to finish. Use isnan() instead of my unorderedFP() function Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand arch/mips/isa/operands.isa: add more operands for special control regs in int and FP regfiles arch/mips/isa/formats/branch.isa: use R31 instead of r31 arch/mips/isa/formats/fp.isa: use MakeCCVector to set Condition Codes in FCSR arch/mips/regfile/float_regfile.hh: treat control regs like any other reg. Just Index them after the regular architectural registers arch/mips/regfile/int_regfile.hh: treat hi,lo as regular int. regs w/special indexing arch/mips/regfile/regfile.hh: no longer need for special register accesses with their own function. --HG-- rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e
88 lines
2.1 KiB
C++
88 lines
2.1 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Base class for MIPS instructions, and some support functions
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//
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//Outputs to decoder.hh
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output header {{
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using namespace MipsISA;
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/**
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* Base class for all MIPS static instructions.
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*/
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class MipsStaticInst : public StaticInst
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{
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protected:
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/// Make MipsISA register dependence tags directly visible in
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/// this class and derived classes. Maybe these should really
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/// live here and not in the MipsISA namespace.
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/*enum DependenceTags {
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FP_Base_DepTag = MipsISA::FP_Base_DepTag,
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Fpcr_DepTag = MipsISA::Fpcr_DepTag,
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Uniq_DepTag = MipsISA::Uniq_DepTag,
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IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
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};*/
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// Constructor
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MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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}
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/// Print a register name for disassembly given the unique
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/// dependence tag number (FP or int).
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void printReg(std::ostream &os, int reg) const;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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//Ouputs to decoder.cc
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output decoder {{
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void MipsStaticInst::printReg(std::ostream &os, int reg) const
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{
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if (reg < FP_Base_DepTag) {
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ccprintf(os, "r%d", reg);
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}
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else {
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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}
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}
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std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if(_numDestRegs > 0){
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printReg(ss, _destRegIdx[0]);
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}
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if(_numSrcRegs > 0) {
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ss << ",";
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printReg(ss, _srcRegIdx[0]);
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}
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if(_numSrcRegs > 1) {
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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if(mnemonic == "sll" || mnemonic == "sra"){
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ccprintf(ss,", %d",SA);
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}
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return ss.str();
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}
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}};
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