72538294fb
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
200 lines
6.7 KiB
C++
200 lines
6.7 KiB
C++
/*
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* Copyright (c) 2007-2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/regs/float.hh"
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#include "arch/x86/regs/int.hh"
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#include "arch/x86/isa_traits.hh"
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#include "arch/x86/nativetrace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/ExecRegDelta.hh"
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#include "params/X86NativeTrace.hh"
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#include "sim/byteswap.hh"
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namespace Trace {
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void
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X86NativeTrace::ThreadState::update(NativeTrace *parent)
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{
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parent->read(this, sizeof(*this));
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rax = X86ISA::gtoh(rax);
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rcx = X86ISA::gtoh(rcx);
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rdx = X86ISA::gtoh(rdx);
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rbx = X86ISA::gtoh(rbx);
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rsp = X86ISA::gtoh(rsp);
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rbp = X86ISA::gtoh(rbp);
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rsi = X86ISA::gtoh(rsi);
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rdi = X86ISA::gtoh(rdi);
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r8 = X86ISA::gtoh(r8);
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r9 = X86ISA::gtoh(r9);
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r10 = X86ISA::gtoh(r10);
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r11 = X86ISA::gtoh(r11);
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r12 = X86ISA::gtoh(r12);
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r13 = X86ISA::gtoh(r13);
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r14 = X86ISA::gtoh(r14);
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r15 = X86ISA::gtoh(r15);
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rip = X86ISA::gtoh(rip);
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//This should be expanded if x87 registers are considered
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for (int i = 0; i < 8; i++)
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mmx[i] = X86ISA::gtoh(mmx[i]);
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for (int i = 0; i < 32; i++)
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xmm[i] = X86ISA::gtoh(xmm[i]);
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}
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void
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X86NativeTrace::ThreadState::update(ThreadContext *tc)
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{
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rax = tc->readIntReg(X86ISA::INTREG_RAX);
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rcx = tc->readIntReg(X86ISA::INTREG_RCX);
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rdx = tc->readIntReg(X86ISA::INTREG_RDX);
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rbx = tc->readIntReg(X86ISA::INTREG_RBX);
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rsp = tc->readIntReg(X86ISA::INTREG_RSP);
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rbp = tc->readIntReg(X86ISA::INTREG_RBP);
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rsi = tc->readIntReg(X86ISA::INTREG_RSI);
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rdi = tc->readIntReg(X86ISA::INTREG_RDI);
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r8 = tc->readIntReg(X86ISA::INTREG_R8);
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r9 = tc->readIntReg(X86ISA::INTREG_R9);
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r10 = tc->readIntReg(X86ISA::INTREG_R10);
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r11 = tc->readIntReg(X86ISA::INTREG_R11);
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r12 = tc->readIntReg(X86ISA::INTREG_R12);
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r13 = tc->readIntReg(X86ISA::INTREG_R13);
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r14 = tc->readIntReg(X86ISA::INTREG_R14);
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r15 = tc->readIntReg(X86ISA::INTREG_R15);
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rip = tc->pcState().npc();
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//This should be expanded if x87 registers are considered
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for (int i = 0; i < 8; i++)
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mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
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for (int i = 0; i < 32; i++)
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xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
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}
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X86NativeTrace::X86NativeTrace(const Params *p)
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: NativeTrace(p)
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{
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checkRcx = true;
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checkR11 = true;
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}
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bool
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X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
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{
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if(!checkRcx)
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checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
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if(checkRcx)
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return checkReg(name, mVal, nVal);
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return true;
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}
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bool
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X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
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{
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if(!checkR11)
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checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
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if(checkR11)
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return checkReg(name, mVal, nVal);
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return true;
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}
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bool
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X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
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{
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if (mXmmBuf[num * 2] != nXmmBuf[num * 2] ||
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mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
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DPRINTF(ExecRegDelta,
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"Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
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num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
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mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
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return false;
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}
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return true;
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}
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void
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X86NativeTrace::check(NativeTraceRecord *record)
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{
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nState.update(this);
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mState.update(record->getThread());
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if(record->getStaticInst()->isSyscall())
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{
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checkRcx = false;
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checkR11 = false;
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oldRcxVal = mState.rcx;
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oldRealRcxVal = nState.rcx;
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oldR11Val = mState.r11;
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oldRealR11Val = nState.r11;
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}
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checkReg("rax", mState.rax, nState.rax);
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checkRcxReg("rcx", mState.rcx, nState.rcx);
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checkReg("rdx", mState.rdx, nState.rdx);
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checkReg("rbx", mState.rbx, nState.rbx);
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checkReg("rsp", mState.rsp, nState.rsp);
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checkReg("rbp", mState.rbp, nState.rbp);
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checkReg("rsi", mState.rsi, nState.rsi);
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checkReg("rdi", mState.rdi, nState.rdi);
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checkReg("r8", mState.r8, nState.r8);
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checkReg("r9", mState.r9, nState.r9);
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checkReg("r10", mState.r10, nState.r10);
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checkR11Reg("r11", mState.r11, nState.r11);
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checkReg("r12", mState.r12, nState.r12);
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checkReg("r13", mState.r13, nState.r13);
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checkReg("r14", mState.r14, nState.r14);
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checkReg("r15", mState.r15, nState.r15);
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checkReg("rip", mState.rip, nState.rip);
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checkXMM(0, mState.xmm, nState.xmm);
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checkXMM(1, mState.xmm, nState.xmm);
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checkXMM(2, mState.xmm, nState.xmm);
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checkXMM(3, mState.xmm, nState.xmm);
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checkXMM(4, mState.xmm, nState.xmm);
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checkXMM(5, mState.xmm, nState.xmm);
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checkXMM(6, mState.xmm, nState.xmm);
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checkXMM(7, mState.xmm, nState.xmm);
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checkXMM(8, mState.xmm, nState.xmm);
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checkXMM(9, mState.xmm, nState.xmm);
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checkXMM(10, mState.xmm, nState.xmm);
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checkXMM(11, mState.xmm, nState.xmm);
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checkXMM(12, mState.xmm, nState.xmm);
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checkXMM(13, mState.xmm, nState.xmm);
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checkXMM(14, mState.xmm, nState.xmm);
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checkXMM(15, mState.xmm, nState.xmm);
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}
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} // namespace Trace
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////////////////////////////////////////////////////////////////////////
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//
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// ExeTracer Simulation Object
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//
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Trace::X86NativeTrace *
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X86NativeTraceParams::create()
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{
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return new Trace::X86NativeTrace(this);
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}
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