Korey Sewell a48c24b61e Support NNPC and branch instructions ... Outputs to decoder.cc correctly ... Edits to the CPU model may still need to be made to handle branch likely insts... arch/isa_parser.py: add a NNPC operand ... arch/mips/isa/base.isa: change SPARC to MIPS arch/mips/isa/decoder.isa: typo < to >= arch/mips/isa/formats/basic.isa: spacing arch/mips/isa/formats/branch.isa: add code for branch instructions (still need adjustments for the branch likely) arch/mips/isa/operands.isa: support for NNPC and R31 arch/mips/isa_traits.hh: NNPC Addr variable --HG-- extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad		2006-02-18 23:17:45 -05:00
..
formats	Support NNPC and branch instructions ... Outputs to decoder.cc correctly	2006-02-18 23:17:45 -05:00
base.isa	Support NNPC and branch instructions ... Outputs to decoder.cc correctly	2006-02-18 23:17:45 -05:00
bitfields.isa	make MIPS MT instructions decodable ...	2006-02-14 02:03:14 -05:00
decoder.isa	Support NNPC and branch instructions ... Outputs to decoder.cc correctly	2006-02-18 23:17:45 -05:00
formats.isa	MIPS generates ISA code through scons '.../decoder.cc'!!!	2006-02-18 03:12:04 -05:00
includes.isa	name changes ... minor IntOP format change	2006-02-07 18:36:08 -05:00
main.isa	trying to get ISA to parse correctly ...	2006-02-14 21:26:01 -05:00
operands.isa	Support NNPC and branch instructions ... Outputs to decoder.cc correctly	2006-02-18 23:17:45 -05:00