1537 lines
183 KiB
Text
1537 lines
183 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.903737 # Number of seconds simulated
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sim_ticks 2903736790500 # Number of ticks simulated
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final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 515424 # Simulator instruction rate (inst/s)
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host_op_rate 621448 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 13306386787 # Simulator tick rate (ticks/s)
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host_mem_usage 582748 # Number of bytes of host memory used
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host_seconds 218.22 # Real time elapsed on the host
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sim_insts 112476413 # Number of instructions simulated
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sim_ops 135613231 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 168642 # Number of read requests accepted
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system.physmem.writeReqs 123424 # Number of write requests accepted
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system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9943 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9648 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10560 # Per bank write bursts
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system.physmem.perBankRdBursts::3 10245 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18706 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9867 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9999 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10271 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9694 # Per bank write bursts
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system.physmem.perBankRdBursts::9 10419 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9828 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9028 # Per bank write bursts
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system.physmem.perBankRdBursts::12 10140 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10489 # Per bank write bursts
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system.physmem.perBankRdBursts::14 10151 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9508 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7397 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7199 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8385 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7801 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7213 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7134 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7314 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7590 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7388 # Per bank write bursts
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system.physmem.perBankWrBursts::9 8015 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7407 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6899 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7622 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7751 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7507 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6882 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
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system.physmem.totGap 2903736355000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 9558 # Read request sizes (log2)
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system.physmem.readPktSize::3 14 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 159070 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4381 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 119043 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1493636250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 138583 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 90798 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 9942055.41 # Average gap between requests
|
|
system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 669.487777 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 669.396712 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dtb.walker.walks 9520 # Table walker walks requested
|
|
system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors
|
|
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 24525489 # DTB read hits
|
|
system.cpu.dtb.read_misses 8109 # DTB read misses
|
|
system.cpu.dtb.write_hits 19608938 # DTB write hits
|
|
system.cpu.dtb.write_misses 1411 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 24533598 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 19610349 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 44134427 # DTB hits
|
|
system.cpu.dtb.misses 9520 # DTB misses
|
|
system.cpu.dtb.accesses 44143947 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.itb.walker.walks 4762 # Table walker walks requested
|
|
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
|
|
system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 115574516 # ITB inst hits
|
|
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 115579278 # ITB inst accesses
|
|
system.cpu.itb.hits 115574516 # DTB hits
|
|
system.cpu.itb.misses 4762 # DTB misses
|
|
system.cpu.itb.accesses 115579278 # DTB accesses
|
|
system.cpu.numPwrStateTransitions 6062 # Number of power state transitions
|
|
system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state
|
|
system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states
|
|
system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 5807473581 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed
|
|
system.cpu.committedInsts 112476413 # Number of instructions committed
|
|
system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
|
|
system.cpu.num_func_calls 9896179 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 119916333 # number of integer instructions
|
|
system.cpu.num_fp_insts 11161 # number of float instructions
|
|
system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 45414800 # number of memory refs
|
|
system.cpu.num_load_insts 24847736 # Number of load instructions
|
|
system.cpu.num_store_insts 20567064 # Number of store instructions
|
|
system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.927161 # Percentage of idle cycles
|
|
system.cpu.Branches 25923023 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 138734340 # Class of executed instruction
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 819770 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 42336572 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 698813 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 698813 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 817273 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 817273 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5967732500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5967732500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12596392000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 12596392000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280149500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 280149500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 18564124500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 18564124500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 18564124500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 18564124500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23517618 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 23517618 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19125003 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19125003 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511224 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 511224 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466060 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 466060 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460279 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 460279 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 42642621 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 42642621 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 43153845 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 43153845 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017011 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.017011 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015621 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.015621 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231718 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.231718 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048588 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048588 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.016388 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.016388 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.018939 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.018939 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.224888 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 26565.224888 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 683946 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 399381 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298752 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 298752 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116429 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 116429 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8499 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8499 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 698133 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 698133 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 814562 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 814562 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5555392000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5555392000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12297640000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12297640000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1530002500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1530002500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 108858500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108858500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17853032000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 17853032000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227746 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227746 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018236 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018236 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016372 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016372 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018876 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.018876 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13910.005734 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25572.537038 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25572.537038 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23795.652756 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23795.652756 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201721.546021 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.546021 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 1698000 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997517 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997517 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 113875998 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1698518 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks
|
|
system.cpu.icache.writebacks::total 1698000 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 89464 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9524.120186 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 55489.656162 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145327 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.846705 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.992091 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65407 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60798 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998032 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 40230644 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 40230644 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5114 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2743 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 7857 # number of ReadReq hits
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 683946 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 683946 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 1666952 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 1666952 # number of WritebackClean hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2730 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 2730 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 166687 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 166687 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1680478 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1680478 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 512210 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 512210 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 5114 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 2743 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1680478 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 678897 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2367232 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 5114 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 2743 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1680478 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 678897 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2367232 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 8 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 10 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 129315 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 129315 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18016 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 18016 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12099 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 12099 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 8 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 18016 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 141414 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 159440 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 8 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 18016 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 141414 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 159440 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 829500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 168000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 997500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 581000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10066469000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10066469000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1464060500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1464060500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1012302000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1012302000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 829500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 168000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1464060500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11078771000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 12543829000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 829500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 168000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1464060500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11078771000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 12543829000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5122 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2745 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7867 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 683946 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 683946 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666952 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 1666952 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2750 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2750 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 296002 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 296002 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1698494 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1698494 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 524309 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 524309 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5122 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2745 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1698494 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 820311 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2526672 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5122 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2745 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1698494 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 820311 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2526672 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001562 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000729 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001271 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.007273 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.007273 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436872 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436872 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010607 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001562 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000729 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.172391 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.063103 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001562 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000729 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.172391 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.063103 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103687.500000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 99750 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29050 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29050 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77844.557863 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77844.557863 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81264.459369 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81264.459369 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83668.237044 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83668.237044 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 78674.291269 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 78674.291269 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.writebacks::writebacks 82853 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 82853 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 8 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129315 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 129315 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18016 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18016 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12099 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12099 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 8 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 18016 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 141414 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 159440 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 8 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18016 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 141414 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 159440 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 749500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 148000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 897500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 381000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 381000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8773319000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8773319000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1283900500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1283900500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 891312000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 891312000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 148000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1283900500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9664631000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10949429000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 749500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 148000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1283900500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9664631000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10949429000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 574512000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5891860500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6466372500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 574512000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5891860500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6466372500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001271 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.007273 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.007273 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436872 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 113519 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.iocache.tags.replacements 36424 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328122 # Number of data accesses
|
|
system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 36458 # number of overall misses
|
|
system.iocache.overall_misses::total 36458 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency
|
|
system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 70519 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 6845 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 129207 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 129207 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 498 # Total snoops (count)
|
|
system.membus.snoopTraffic 31744 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 263669 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 263669 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states
|
|
|
|
---------- End Simulation Statistics ----------
|