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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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---------- Begin Simulation Statistics ----------
sim_seconds 2.804117 # Number of seconds simulated
sim_ticks 2804116777000 # Number of ticks simulated
final_tick 2804116777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 79056 # Simulator instruction rate (inst/s)
host_op_rate 95953 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1895501031 # Simulator tick rate (ticks/s)
host_mem_usage 624156 # Number of bytes of host memory used
host_seconds 1479.35 # Real time elapsed on the host
sim_insts 116952036 # Number of instructions simulated
sim_ops 141948815 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 4480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 698944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4896096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 4480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 676224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4916296 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 11197544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 698944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 676224 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1375168 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8445824 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
system.physmem.bytes_written::total 8463348 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 70 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 10921 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 77020 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 70 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10566 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 76819 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 175482 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131966 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
system.physmem.num_writes::total 136347 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 249256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1746039 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 241154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1753242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3993252 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 249256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 241154 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 490410 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3011937 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6247 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3018187 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3011937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 249256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1752285 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 241154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1753245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7011438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 175483 # Number of read requests accepted
system.physmem.writeReqs 136347 # Number of write requests accepted
system.physmem.readBursts 175483 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 136347 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11221120 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue
system.physmem.bytesWritten 8475904 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11197608 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8463348 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3889 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 40841 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11242 # Per bank write bursts
system.physmem.perBankRdBursts::1 11247 # Per bank write bursts
system.physmem.perBankRdBursts::2 11589 # Per bank write bursts
system.physmem.perBankRdBursts::3 11122 # Per bank write bursts
system.physmem.perBankRdBursts::4 11335 # Per bank write bursts
system.physmem.perBankRdBursts::5 11409 # Per bank write bursts
system.physmem.perBankRdBursts::6 11590 # Per bank write bursts
system.physmem.perBankRdBursts::7 11844 # Per bank write bursts
system.physmem.perBankRdBursts::8 10538 # Per bank write bursts
system.physmem.perBankRdBursts::9 10661 # Per bank write bursts
system.physmem.perBankRdBursts::10 10504 # Per bank write bursts
system.physmem.perBankRdBursts::11 9563 # Per bank write bursts
system.physmem.perBankRdBursts::12 10483 # Per bank write bursts
system.physmem.perBankRdBursts::13 10932 # Per bank write bursts
system.physmem.perBankRdBursts::14 10755 # Per bank write bursts
system.physmem.perBankRdBursts::15 10516 # Per bank write bursts
system.physmem.perBankWrBursts::0 8424 # Per bank write bursts
system.physmem.perBankWrBursts::1 8579 # Per bank write bursts
system.physmem.perBankWrBursts::2 8987 # Per bank write bursts
system.physmem.perBankWrBursts::3 8481 # Per bank write bursts
system.physmem.perBankWrBursts::4 8341 # Per bank write bursts
system.physmem.perBankWrBursts::5 8592 # Per bank write bursts
system.physmem.perBankWrBursts::6 8708 # Per bank write bursts
system.physmem.perBankWrBursts::7 8869 # Per bank write bursts
system.physmem.perBankWrBursts::8 8028 # Per bank write bursts
system.physmem.perBankWrBursts::9 8030 # Per bank write bursts
system.physmem.perBankWrBursts::10 7878 # Per bank write bursts
system.physmem.perBankWrBursts::11 7235 # Per bank write bursts
system.physmem.perBankWrBursts::12 7993 # Per bank write bursts
system.physmem.perBankWrBursts::13 8331 # Per bank write bursts
system.physmem.perBankWrBursts::14 8147 # Per bank write bursts
system.physmem.perBankWrBursts::15 7813 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 2804116613000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 174927 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 131966 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 103653 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 61646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1700 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2079 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2539 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4972 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6688 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 9719 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9024 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8820 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7947 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 303.152399 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 178.671137 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 326.237503 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24321 37.43% 37.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15991 24.61% 62.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6608 10.17% 72.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3730 5.74% 77.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2732 4.20% 82.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1666 2.56% 84.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1104 1.70% 86.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1133 1.74% 88.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7689 11.83% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64974 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6726 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.057835 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 476.710834 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6724 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6726 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6726 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.690158 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.212427 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 11.515810 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 4 0.06% 0.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 7 0.10% 0.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 10 0.15% 0.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5748 85.46% 86.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 152 2.26% 88.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 195 2.90% 91.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 73 1.09% 92.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 81 1.20% 93.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 162 2.41% 95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 28 0.42% 96.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 11 0.16% 96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 17 0.25% 96.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 10 0.15% 96.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 8 0.12% 96.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.12% 97.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 154 2.29% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.07% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.07% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 6 0.09% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 3 0.04% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.01% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 11 0.16% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.04% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6726 # Writes before turning the bus around for reads
system.physmem.totQLat 2656155250 # Total ticks spent queuing
system.physmem.totMemAccLat 5943592750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 876650000 # Total ticks spent in databus transfers
system.physmem.avgQLat 15149.38 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 33899.27 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing
system.physmem.avgWrQLen 10.62 # Average write queue length when enqueuing
system.physmem.readRowHits 144959 # Number of row buffer hits during reads
system.physmem.writeRowHits 97833 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.86 # Row buffer hit rate for writes
system.physmem.avgGap 8992452.98 # Average gap between requests
system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 259035840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 141339000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 712748400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 446996880 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 183151272720 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 77780216115 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1614241917750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1876733526705 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.277905 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2685339699500 # Time in different power states
system.physmem_0.memoryStateTime::REF 93635360000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 25141656750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 232167600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 126678750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654825600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 411188400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 183151272720 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 76668937560 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1615216723500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1876461794130 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.181000 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2686967028000 # Time in different power states
system.physmem_1.memoryStateTime::REF 93635360000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 23514328250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 26869227 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13991642 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 524467 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 16420293 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 12603750 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 76.757157 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 6640393 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 27621 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 57399 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 57399 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17473 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14797 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 25129 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 32270 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 687.186241 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 4502.840845 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383 31894 98.83% 98.83% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767 274 0.85% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151 54 0.17% 99.85% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919 17 0.05% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-147455 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 32270 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 12902 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12660.750271 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10400.452854 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 8033.389954 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 9915 76.85% 76.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 2761 21.40% 98.25% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 203 1.57% 99.82% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.05% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 14 0.11% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 12902 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 76391677040 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.743538 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.460978 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 76311291040 99.89% 99.89% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 56342500 0.07% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 12108500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 4568500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 2307500 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 1375000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 973000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 1821000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 435000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 132000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21 55000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23 49500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25 144000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29 8500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31 51500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 76391677040 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 3747 70.16% 70.16% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1594 29.84% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 5341 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 57399 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 57399 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5341 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5341 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 62740 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 14047287 # DTB read hits
system.cpu0.dtb.read_misses 49327 # DTB read misses
system.cpu0.dtb.write_hits 10317828 # DTB write hits
system.cpu0.dtb.write_misses 8072 # DTB write misses
system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 482 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 817 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1439 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 14096614 # DTB read accesses
system.cpu0.dtb.write_accesses 10325900 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 24365115 # DTB hits
system.cpu0.dtb.misses 57399 # DTB misses
system.cpu0.dtb.accesses 24422514 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 7905 # Table walker walks requested
system.cpu0.itb.walker.walksShort 7905 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2649 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5113 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 143 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 7762 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1462.316413 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 6006.318105 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-8191 7298 94.02% 94.02% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-16383 191 2.46% 96.48% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-24575 163 2.10% 98.58% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-32767 55 0.71% 99.29% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-40959 14 0.18% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-49151 16 0.21% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::57344-65535 7 0.09% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-73727 3 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-90111 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 7762 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2523 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13374.950456 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11026.619167 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 8136.408829 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 825 32.70% 32.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 999 39.60% 72.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 627 24.85% 97.15% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 25 0.99% 98.14% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 16 0.63% 98.77% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 27 1.07% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2523 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 33438392080 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.922681 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.267784 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 2590170000 7.75% 7.75% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 30844665580 92.24% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 2600500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 732500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 223500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 33438392080 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1818 76.39% 76.39% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 562 23.61% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2380 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7905 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7905 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2380 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2380 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 10285 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 20120654 # ITB inst hits
system.cpu0.itb.inst_misses 7905 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 482 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2326 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 20128559 # ITB inst accesses
system.cpu0.itb.hits 20120654 # DTB hits
system.cpu0.itb.misses 7905 # DTB misses
system.cpu0.itb.accesses 20128559 # DTB accesses
system.cpu0.numCycles 106084335 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 39806494 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 103893687 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 26869227 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 19244143 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 61681241 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3154924 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 126092 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 4609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 416 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 201724 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 122006 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 20119405 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 359114 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3525 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 103520405 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.205881 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.305845 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 74908218 72.36% 72.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 3833241 3.70% 76.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 2379626 2.30% 78.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 8018936 7.75% 86.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1633248 1.58% 87.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 1022119 0.99% 88.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 6115753 5.91% 94.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 1028201 0.99% 95.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4581063 4.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 103520405 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.253282 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.979350 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 27459073 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 57640843 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 15538578 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1452555 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1429102 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1871474 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 150372 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 86076544 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 485871 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1429102 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 28294007 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 6612104 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 43619414 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 16146294 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 7419215 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 82346799 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 3179 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1065744 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 299526 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 5341738 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 84890721 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 379205899 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 91831678 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 6335 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 71376559 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13514162 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1526597 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1432651 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8443957 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 14885891 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 11404400 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1982860 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2750757 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 79215613 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1056336 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 75904646 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 90770 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 11089379 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 24203913 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 112312 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 103520405 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.733234 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.426738 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 73282727 70.79% 70.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10008412 9.67% 80.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 7714570 7.45% 87.91% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 6465771 6.25% 94.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2339617 2.26% 96.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1485866 1.44% 97.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 1511901 1.46% 99.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 481751 0.47% 99.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 229790 0.22% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 103520405 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 105175 9.45% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 1 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 531702 47.76% 57.20% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 476475 42.80% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2185 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 50511411 66.55% 66.55% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 57825 0.08% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 5 0.00% 66.62% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 4290 0.01% 66.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 14447360 19.03% 85.66% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 10881568 14.34% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 75904646 # Type of FU issued
system.cpu0.iq.rate 0.715512 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1113353 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.014668 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 256519810 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 91406915 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 73615254 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 14010 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 7412 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 6126 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 77008290 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 7524 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 368125 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2165393 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 54160 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1099887 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 208534 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 95734 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1429102 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 5759594 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 639314 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 80435080 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 122511 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 14885891 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 11404400 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 549713 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 48457 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 578413 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 54160 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 234602 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 214611 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 449213 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 75318249 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 14211760 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 529106 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 163131 # number of nop insts executed
system.cpu0.iew.exec_refs 24990941 # number of memory reference insts executed
system.cpu0.iew.exec_branches 14215836 # Number of branches executed
system.cpu0.iew.exec_stores 10779181 # Number of stores executed
system.cpu0.iew.exec_rate 0.709985 # Inst execution rate
system.cpu0.iew.wb_sent 74778323 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 73621380 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 38389560 # num instructions producing a value
system.cpu0.iew.wb_consumers 66627447 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.693989 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.576182 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 11066735 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 944024 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 376070 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 101026787 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.685770 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.579563 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 74129277 73.38% 73.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 12088684 11.97% 85.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 6100635 6.04% 91.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2597407 2.57% 93.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1266923 1.25% 95.21% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 835295 0.83% 96.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1855576 1.84% 97.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 402562 0.40% 98.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1750428 1.73% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 101026787 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 57027520 # Number of instructions committed
system.cpu0.commit.committedOps 69281156 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 23025011 # Number of memory references committed
system.cpu0.commit.loads 12720498 # Number of loads committed
system.cpu0.commit.membars 379883 # Number of memory barriers committed
system.cpu0.commit.branches 13454174 # Number of branches committed
system.cpu0.commit.fp_insts 6046 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 60620890 # Number of committed integer instructions.
system.cpu0.commit.function_calls 2622879 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 46195742 66.68% 66.68% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 56117 0.08% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 4286 0.01% 66.77% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 12720498 18.36% 85.13% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 10304513 14.87% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 69281156 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1750428 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 167227208 # The number of ROB reads
system.cpu0.rob.rob_writes 163193530 # The number of ROB writes
system.cpu0.timesIdled 392212 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 2563930 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2956294180 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 56928934 # Number of Instructions Simulated
system.cpu0.committedOps 69182570 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.863452 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.863452 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.536638 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.536638 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 81967291 # number of integer regfile reads
system.cpu0.int_regfile_writes 46848639 # number of integer regfile writes
system.cpu0.fp_regfile_reads 16893 # number of floating regfile reads
system.cpu0.fp_regfile_writes 13046 # number of floating regfile writes
system.cpu0.cc_regfile_reads 266506484 # number of cc regfile reads
system.cpu0.cc_regfile_writes 27807772 # number of cc regfile writes
system.cpu0.misc_regfile_reads 144531551 # number of misc regfile reads
system.cpu0.misc_regfile_writes 724861 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 854304 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.982090 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 42365382 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 854816 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 49.560820 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 105251500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.651423 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 325.330668 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.364554 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.635411 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 189302421 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189302421 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 12461175 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 12728962 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25190137 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 7687590 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 8214972 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15902562 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 179184 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 184541 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 363725 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210025 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236354 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 446379 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216363 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243044 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459407 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20148765 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 20943934 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41092699 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20327949 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21128475 # number of overall hits
system.cpu0.dcache.overall_hits::total 41456424 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 423956 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 411527 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 835483 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1938723 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1762743 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 3701466 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 85809 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 99027 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 184836 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13675 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14161 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 27836 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 25 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 39 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 64 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2362679 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 2174270 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4536949 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2448488 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 2273297 # number of overall misses
system.cpu0.dcache.overall_misses::total 4721785 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6233091500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6311528000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 12544619500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 83629442032 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 80611512663 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 164240954695 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 181225000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 207964000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 389189000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 566500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 630000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 1196500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 89862533532 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 86923040663 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 176785574195 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 89862533532 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 86923040663 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 176785574195 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 12885131 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 13140489 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26025620 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9626313 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9977715 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19604028 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 264993 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 283568 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 548561 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223700 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250515 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 474215 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216388 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243083 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459471 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 22511444 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 23118204 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 45629648 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 22776437 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 23401772 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 46178209 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032903 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031317 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.032102 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.201398 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.176668 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.188812 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323816 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.349218 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336947 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061131 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056528 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058699 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000116 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000160 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000139 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.104955 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.094050 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.099430 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107501 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097142 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.102251 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14702.213201 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15336.850316 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15014.811193 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43136.354204 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45730.723459 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44371.866362 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13252.285192 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14685.686039 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13981.498779 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22660 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16153.846154 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18695.312500 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38034.169488 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39978.034312 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 38965.739795 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36701.235020 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 38236.552753 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37440.411665 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1130992 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 181993 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 52749 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 2872 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.441013 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 63.368036 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 704468 # number of writebacks
system.cpu0.dcache.writebacks::total 704468 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 206826 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 203538 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 410364 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1782978 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1618509 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3401487 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9580 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9255 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18835 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1989804 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1822047 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3811851 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1989804 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1822047 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3811851 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217130 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 207989 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 425119 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155745 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 144234 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 299979 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 58865 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64694 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 123559 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4095 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4906 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9001 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 25 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 39 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 64 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 372875 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 352223 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 725098 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 431740 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 416917 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 848657 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16525 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14602 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16127 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11457 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32652 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 26059 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3060881000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3004845500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6065726500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7052803399 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6808261422 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13861064821 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 813215500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 923997500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737213000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53086000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81449000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 134535000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 541500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 591000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1132500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10113684399 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9813106922 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 19926791321 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10926899899 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10737104422 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 21664004321 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3144537000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2771379000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5915916000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2402448877 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2170311500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572760377 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5546985877 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4941690500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10488676377 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016851 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015828 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016335 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016179 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014456 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015302 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222138 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228143 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225242 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018306 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019584 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018981 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000116 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000160 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000139 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016564 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015236 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.015891 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018956 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017816 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018378 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14096.997191 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14447.136627 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14268.302522 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45284.300613 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47202.888514 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46206.783878 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13814.923979 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14282.584165 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14059.785204 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12963.614164 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16601.916021 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14946.672592 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21660 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15153.846154 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17695.312500 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27123.525039 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27860.494408 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27481.514666 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25308.982024 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25753.577863 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25527.397195 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190289.682300 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189794.480208 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.377839 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148970.600670 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189431.046522 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.825732 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169881.963647 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189634.694347 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.254433 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1933259 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.562237 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 38860881 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1933771 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 20.095906 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 9655718500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 227.659514 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 283.902722 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.444647 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.554498 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999145 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 42875303 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 42875303 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 19083138 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 19777743 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 38860881 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 19083138 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 19777743 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 38860881 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 19083138 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 19777743 # number of overall hits
system.cpu0.icache.overall_hits::total 38860881 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1035596 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1044946 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 2080542 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1035596 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1044946 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 2080542 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1035596 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1044946 # number of overall misses
system.cpu0.icache.overall_misses::total 2080542 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13933067983 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14083489486 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 28016557469 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13933067983 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 14083489486 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 28016557469 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13933067983 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 14083489486 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 28016557469 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 20118734 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20822689 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 40941423 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 20118734 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 20822689 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 40941423 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 20118734 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 20822689 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 40941423 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051474 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050183 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050818 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051474 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050183 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050818 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051474 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050183 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050818 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13454.153920 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.719888 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13465.989857 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13454.153920 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13477.719888 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13465.989857 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13454.153920 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13477.719888 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13465.989857 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 11261 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 589 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.118846 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72785 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 73876 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 146661 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 72785 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 73876 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 146661 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 72785 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 73876 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 146661 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 962811 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 971070 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1933881 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 962811 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 971070 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1933881 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 962811 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 971070 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1933881 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 670 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 670 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 670 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 670 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12308964487 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12437182489 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 24746146976 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12308964487 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12437182489 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 24746146976 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12308964487 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12437182489 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 24746146976 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52946500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52946500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52946500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 52946500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047235 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.047235 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047856 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046635 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.047235 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12796.106366 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12796.106366 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12784.403675 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.709526 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12796.106366 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79024.626866 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79024.626866 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 27575669 # Number of BP lookups
system.cpu1.branchPred.condPredicted 14289271 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 524894 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 17274855 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 12959236 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 75.017915 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 6858393 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 28646 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 57029 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 57029 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18821 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 12862 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 25346 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 31683 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 591.216110 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3688.783466 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383 31359 98.98% 98.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767 255 0.80% 99.78% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151 48 0.15% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535 10 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919 7 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 31683 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 12352 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12478.424547 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10246.973289 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 7685.568959 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 3962 32.08% 32.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5577 45.15% 77.23% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2494 20.19% 97.42% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 102 0.83% 98.24% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 90 0.73% 98.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 118 0.96% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 12352 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 89696770428 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.667017 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.494297 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 89674974428 99.98% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7 14056500 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11 3500500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15 2366000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19 661500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23 722500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27 410000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31 58000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35 21000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 89696770428 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 3380 68.04% 68.04% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 1588 31.96% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 4968 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 57029 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 57029 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4968 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4968 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 61997 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 14318727 # DTB read hits
system.cpu1.dtb.read_misses 47357 # DTB read misses
system.cpu1.dtb.write_hits 10661439 # DTB write hits
system.cpu1.dtb.write_misses 9672 # DTB write misses
system.cpu1.dtb.flush_tlb 177 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 435 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 3458 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 745 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 1189 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 539 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 14366084 # DTB read accesses
system.cpu1.dtb.write_accesses 10671111 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 24980166 # DTB hits
system.cpu1.dtb.misses 57029 # DTB misses
system.cpu1.dtb.accesses 25037195 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 7307 # Table walker walks requested
system.cpu1.itb.walker.walksShort 7307 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2390 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4761 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 156 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 7151 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1572.647182 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 6795.072359 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191 6710 93.83% 93.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383 190 2.66% 96.49% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575 127 1.78% 98.27% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767 50 0.70% 98.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959 21 0.29% 99.26% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151 20 0.28% 99.54% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343 12 0.17% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535 7 0.10% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::90112-98303 3 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-106495 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 7151 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 2506 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 14007.980846 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11793.815638 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 8015.636923 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 694 27.69% 27.69% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1049 41.86% 69.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 688 27.45% 97.01% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 39 1.56% 98.56% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 20 0.80% 99.36% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 13 0.52% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 2506 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 33862083580 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.923542 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.266537 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 2594238448 7.66% 7.66% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 31264179132 92.33% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 2561000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 759000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 256500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 89500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 33862083580 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 1782 75.83% 75.83% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 568 24.17% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 2350 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7307 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7307 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2350 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2350 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 9657 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 20824521 # ITB inst hits
system.cpu1.itb.inst_misses 7307 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 177 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 435 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2324 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 1310 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 20831828 # ITB inst accesses
system.cpu1.itb.hits 20824521 # DTB hits
system.cpu1.itb.misses 7307 # DTB misses
system.cpu1.itb.accesses 20831828 # DTB accesses
system.cpu1.numCycles 108440670 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 40658841 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 107348372 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 27575669 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 19817629 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 63179196 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3214627 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 116865 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 7302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 337 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 214773 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 119592 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 20822690 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 365691 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3329 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 105904439 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.219564 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.316618 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 76345521 72.09% 72.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 3953421 3.73% 75.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 2478828 2.34% 78.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 8244207 7.78% 85.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1577040 1.49% 87.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 1177168 1.11% 88.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 6267610 5.92% 94.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 1171227 1.11% 95.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4689417 4.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 105904439 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.254293 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.989927 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 27742693 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 59209108 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 15734012 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1761502 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1456830 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1964004 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 152599 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 89283066 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 495711 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1456830 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 28693287 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 4990149 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 46482214 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 16541431 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 7740224 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 85441153 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 1754 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 1703174 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 185824 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 5043602 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 88283625 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 394169118 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 95445176 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 5573 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 75350045 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 12933564 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1608887 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1508528 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 10148655 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 15129586 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 11812866 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 2166416 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 2845057 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 82323765 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1155194 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 79175749 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 89458 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10712710 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 23890163 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 105302 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 105904439 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.747615 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.428343 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 74038259 69.91% 69.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 10747404 10.15% 80.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 8120323 7.67% 87.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 6768186 6.39% 94.12% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 2459889 2.32% 96.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1534209 1.45% 97.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1518475 1.43% 99.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 479862 0.45% 99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 237832 0.22% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 105904439 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 107820 9.57% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 6 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 518879 46.05% 55.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 500179 44.39% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 152 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 53114016 67.08% 67.08% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 58553 0.07% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 2 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 4284 0.01% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.16% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 14709821 18.58% 85.74% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 11288919 14.26% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 79175749 # Type of FU issued
system.cpu1.iq.rate 0.730130 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 1126884 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014233 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 265459723 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 94235106 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 76889252 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 12556 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 6622 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5424 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 80295719 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 6762 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 344779 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2039504 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 2297 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 51237 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1073925 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 189496 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 106526 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1456830 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 3996467 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 749020 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 83580457 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 125116 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 15129586 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 11812866 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 584610 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 40298 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 696432 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 51237 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 238658 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 209145 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 447803 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 78601263 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 14483577 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 517602 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 101498 # number of nop insts executed
system.cpu1.iew.exec_refs 25666157 # number of memory reference insts executed
system.cpu1.iew.exec_branches 14648718 # Number of branches executed
system.cpu1.iew.exec_stores 11182580 # Number of stores executed
system.cpu1.iew.exec_rate 0.724832 # Inst execution rate
system.cpu1.iew.wb_sent 78056908 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 76894676 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 40431219 # num instructions producing a value
system.cpu1.iew.wb_consumers 70987120 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.709094 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.569557 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 10746753 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 1049892 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 374374 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 103429928 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.704076 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.589371 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 75071598 72.58% 72.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 12660376 12.24% 84.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6524786 6.31% 91.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 2717712 2.63% 93.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1422802 1.38% 95.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 934618 0.90% 96.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 1880111 1.82% 97.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 428884 0.41% 98.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1789041 1.73% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 103429928 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 60079421 # Number of instructions committed
system.cpu1.commit.committedOps 72822564 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 23829023 # Number of memory references committed
system.cpu1.commit.loads 13090082 # Number of loads committed
system.cpu1.commit.membars 434438 # Number of memory barriers committed
system.cpu1.commit.branches 13936997 # Number of branches committed
system.cpu1.commit.fp_insts 5382 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 63857795 # Number of committed integer instructions.
system.cpu1.commit.function_calls 2718317 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 48932373 67.19% 67.19% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 56887 0.08% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.27% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 4281 0.01% 67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.28% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 13090082 17.98% 85.25% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 10738941 14.75% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 72822564 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1789041 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 172463469 # The number of ROB reads
system.cpu1.rob.rob_writes 169617134 # The number of ROB writes
system.cpu1.timesIdled 388810 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 2536231 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2437380839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 60023102 # Number of Instructions Simulated
system.cpu1.committedOps 72766245 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.806649 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.806649 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.553511 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.553511 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 85555118 # number of integer regfile reads
system.cpu1.int_regfile_writes 48994368 # number of integer regfile writes
system.cpu1.fp_regfile_reads 16096 # number of floating regfile reads
system.cpu1.fp_regfile_writes 13216 # number of floating regfile writes
system.cpu1.cc_regfile_reads 277440920 # number of cc regfile reads
system.cpu1.cc_regfile_writes 29218779 # number of cc regfile writes
system.cpu1.misc_regfile_reads 148245272 # number of misc regfile reads
system.cpu1.misc_regfile_writes 794768 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 187527447 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36410 # number of replacements
system.iocache.tags.tagsinuse 0.980586 # Cycle average of tags in use
system.iocache.tags.total_refs 29 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000796 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 234074441000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 0.980586 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.061287 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.061287 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328228 # Number of tag accesses
system.iocache.tags.data_accesses 328228 # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide 28 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 28 # number of WriteLineReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36196 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36196 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 30886877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 30886877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4270029570 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4270029570 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 30886877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 30886877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 30886877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 30886877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 0.999227 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 0.999227 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124043.682731 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124043.682731 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117969.653277 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117969.653277 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124043.682731 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124043.682731 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124043.682731 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124043.682731 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36161 # number of writebacks
system.iocache.writebacks::total 36161 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36196 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36196 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18436877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 18436877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460229570 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2460229570 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 18436877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 18436877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 18436877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 18436877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999227 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.999227 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74043.682731 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74043.682731 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67969.653277 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67969.653277 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74043.682731 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74043.682731 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74043.682731 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74043.682731 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 104376 # number of replacements
system.l2c.tags.tagsinuse 65128.447881 # Cycle average of tags in use
system.l2c.tags.total_refs 5130866 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169621 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 30.249002 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 71309274500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 48546.195919 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 40.752142 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4832.971752 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2370.323357 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 46.716496 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 5940.987464 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3350.500506 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.740756 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000622 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.073745 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.036168 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000713 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.090652 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.051125 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993781 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65185 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3268 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 9040 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52500 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994644 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45389875 # Number of tag accesses
system.l2c.tags.data_accesses 45389875 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 34639 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 7724 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 34842 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7429 # number of ReadReq hits
system.l2c.ReadReq_hits::total 84634 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 704468 # number of Writeback hits
system.l2c.Writeback_hits::total 704468 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 46 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 38 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 84 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 83572 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 73244 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 156816 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 952414 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 960356 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1912770 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 273094 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 269324 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 542418 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 34639 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 7724 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 952414 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 356666 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 34842 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7429 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 960356 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 342568 # number of demand (read+write) hits
system.l2c.demand_hits::total 2696638 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 34639 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 7724 # number of overall hits
system.l2c.overall_hits::cpu0.inst 952414 # number of overall hits
system.l2c.overall_hits::cpu0.data 356666 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 34842 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7429 # number of overall hits
system.l2c.overall_hits::cpu1.inst 960356 # number of overall hits
system.l2c.overall_hits::cpu1.data 342568 # number of overall hits
system.l2c.overall_hits::total 2696638 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 70 # number of ReadReq misses
system.l2c.ReadReq_misses::total 141 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1473 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1260 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2733 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 7 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 6 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 13 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 70675 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 69701 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140376 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 10270 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 10574 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 20844 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 6975 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 8256 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 15231 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 70 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 10270 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 77650 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 70 # number of demand (read+write) misses
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system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5524500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 58500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 743672000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 5702270500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 5412000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 772867500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 5718785000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 12948590000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5524500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 58500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 743672000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 5702270500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 5412000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 772867500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 5718785000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 12948590000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 42529000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2937973000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2588853500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5569355500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2214813000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2038551500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4253364500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 42529000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5152786000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4627405000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 9822720000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002017 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000129 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.002005 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.001663 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.969717 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.970724 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.970181 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.280000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.153846 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.203125 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.458194 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.487607 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.472341 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010662 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.010883 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010773 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.024623 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.029530 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002017 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000129 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010662 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.178605 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002005 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010883 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.185240 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.061409 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002017 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000129 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010662 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.178605 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002005 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010883 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.185240 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.061409 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77978.723404 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20778.682960 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20764.682540 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20772.228321 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 35000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 21000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28538.461538 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73240.587195 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72817.542073 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73030.532285 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72802.049830 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76274.941995 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78483.530560 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77474.425230 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73510.338915 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73413.759018 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 73387.647996 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 58500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72454.403741 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73510.338915 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73139.727453 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73413.759018 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 73387.647996 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177789.591528 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177294.445966 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.489323 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137335.710299 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177930.653749 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.798869 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157809.200049 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177574.158640 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.568229 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 31797 # Transaction distribution
system.membus.trans_dist::ReadResp 68110 # Transaction distribution
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::Writeback 131966 # Transaction distribution
system.membus.trans_dist::CleanEvict 8584 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 13 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4648 # Transaction distribution
system.membus.trans_dist::ReadExReq 138475 # Transaction distribution
system.membus.trans_dist::ReadExResp 138475 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 36314 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36195 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36195 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473652 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 581222 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 690052 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17345628 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17509597 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315264 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2315264 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19824861 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 523 # Total snoops (count)
system.membus.snoop_fanout::samples 415806 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 415806 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 415806 # Request fanout histogram
system.membus.reqLayer0.occupancy 95819000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 923516805 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1018756091 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 64465031 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq 148196 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2639888 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 836438 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2043009 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 64 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 297192 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 297192 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1933881 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 557898 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36195 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5760848 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2679672 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 39941 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 161233 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8641694 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123794112 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99989277 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 60616 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 278484 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 224122489 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 209289 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 5932182 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.049498 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.216906 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 5638548 95.05% 95.05% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 293634 4.95% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 5932182 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 3595734997 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 244500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2902818005 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1328890460 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 24804964 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 92041633 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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