1531 lines
177 KiB
Text
1531 lines
177 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.860990 # Number of seconds simulated
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sim_ticks 1860990273000 # Number of ticks simulated
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final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 102674 # Simulator instruction rate (inst/s)
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host_op_rate 102674 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3606509618 # Simulator tick rate (ticks/s)
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host_mem_usage 370916 # Number of bytes of host memory used
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host_seconds 516.01 # Real time elapsed on the host
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sim_insts 52980740 # Number of instructions simulated
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sim_ops 52980740 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 403829 # Number of read requests accepted
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system.physmem.writeReqs 117554 # Number of write requests accepted
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system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25640 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25420 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25567 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25490 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25392 # Per bank write bursts
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system.physmem.perBankRdBursts::5 24736 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24946 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25069 # Per bank write bursts
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system.physmem.perBankRdBursts::8 24934 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25024 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25571 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24874 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24488 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25240 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25741 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25582 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7942 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7515 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7958 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7515 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7335 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6671 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6772 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6705 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7147 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6708 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7414 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6974 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7148 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7857 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8057 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7814 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 22 # Number of times write queue was full causing retry
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system.physmem.totGap 1860985018500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 403829 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 117554 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 3803541750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 364213 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95338 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3569324.31 # Average gap between requests
|
|
system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.266370 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.250855 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 17952495 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 10266725 # DTB read hits
|
|
system.cpu.dtb.read_misses 41420 # DTB read misses
|
|
system.cpu.dtb.read_acv 529 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 965767 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6642195 # DTB write hits
|
|
system.cpu.dtb.write_misses 9809 # DTB write misses
|
|
system.cpu.dtb.write_acv 405 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 342270 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16908920 # DTB hits
|
|
system.cpu.dtb.data_misses 51229 # DTB misses
|
|
system.cpu.dtb.data_acv 934 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1308037 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1768997 # ITB hits
|
|
system.cpu.itb.fetch_misses 27603 # ITB misses
|
|
system.cpu.itb.fetch_acv 655 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1796600 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 122250725 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued
|
|
system.cpu.iq.rate 0.470318 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3688541 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 8971597 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6667115 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.465530 # Inst execution rate
|
|
system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 28741573 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56171345 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15469955 # Number of memory references committed
|
|
system.cpu.commit.loads 9092138 # Number of loads committed
|
|
system.cpu.commit.membars 226307 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8441356 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52021098 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740502 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 56171345 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 2095015 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 177100105 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 129718981 # The number of ROB writes
|
|
system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52980740 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 74560962 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 40515010 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 167029 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167528 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 939256 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 1402429 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 63836458 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 63836458 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7233922 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7233922 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4189857 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4189857 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186093 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 186093 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215697 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215697 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 11423779 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11423779 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 11423779 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11423779 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1801919 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1801919 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1957536 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1957536 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23327 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3759455 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3759455 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3759455 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3759455 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41733061500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 41733061500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 80455809465 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 80455809465 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376093000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 376093000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 485000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 485000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 122188870965 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 122188870965 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 122188870965 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 122188870965 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9035841 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9035841 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6147393 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6147393 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209420 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 209420 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215725 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215725 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15183234 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15183234 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15183234 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15183234 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199419 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.199419 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318434 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.318434 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111389 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111389 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.247606 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.247606 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.247606 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.247606 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23160.342668 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 23160.342668 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41100.551645 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41100.551645 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16122.647576 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16122.647576 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17321.428571 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17321.428571 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 32501.751175 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 32501.751175 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 4515997 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 2303 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 134454 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.587673 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 88.576923 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 841625 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 841625 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 707636 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 707636 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666818 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1666818 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5179 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5179 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2374454 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2374454 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2374454 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2374454 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094283 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1094283 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290718 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 290718 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18148 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 18148 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1385001 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1385001 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1385001 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1385001 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30550296500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30550296500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12634151241 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12634151241 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226327000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226327000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 457000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 457000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43184447741 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 43184447741 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43184447741 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 43184447741 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450758000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450758000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035709998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035709998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486467998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486467998 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121105 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121105 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047291 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047291 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086658 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086658 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091219 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091219 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1038549 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 509.170339 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 7895321 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1039057 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 7.598545 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 28146856500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.170339 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7895322 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1092746 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 220 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.177273 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53320 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 53320 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 53320 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 53320 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 53320 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 53320 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039426 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1039426 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1039426 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1039426 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1039426 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1039426 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13594657497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 13594657497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13594657497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 13594657497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13594657497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 13594657497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115645 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.115645 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.115645 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13079.004659 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13079.004659 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 338316 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65333.743960 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4173914 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 403482 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 10.344734 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 5938026000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 53662.904675 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5355.130521 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6315.708764 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.818831 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081713 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.096370 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996914 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3498 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2393 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 39757135 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 39757135 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 841625 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 841625 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 185982 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 185982 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024048 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1024048 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827700 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 827700 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1024048 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1013682 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2037730 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1024048 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1013682 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2037730 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 98 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 98 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115503 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 115503 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15066 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 15066 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273839 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 273839 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15066 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389342 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404408 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15066 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389342 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404408 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 454500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 454500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 61000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 61000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10302938500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10302938500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1259119000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1259119000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19992285500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 19992285500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1259119000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 30295224000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 31554343000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1259119000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 30295224000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 31554343000 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 841625 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 841625 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 127 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 127 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 301485 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 301485 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039114 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1039114 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101539 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1101539 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1039114 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1403024 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2442138 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1039114 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1403024 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2442138 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.771654 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.771654 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383114 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383114 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014499 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014499 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248597 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248597 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014499 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277502 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.165596 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014499 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277502 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.165596 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4637.755102 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4637.755102 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89200.613837 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89200.613837 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83573.543077 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83573.543077 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73007.444155 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73007.444155 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83573.543077 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.343241 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 78026.010860 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83573.543077 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.343241 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 78026.010860 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 76042 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 76042 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 305 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 305 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 98 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 98 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115503 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115503 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15065 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15065 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273839 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273839 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15065 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389342 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404407 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15065 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389342 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404407 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2195000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2195000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9147908500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9147908500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1108373500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1108373500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17263967500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17263967500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1108373500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26411876000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 27520249500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1108373500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26411876000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 27520249500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364133000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364133000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925339500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925339500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289472500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289472500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.771654 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.771654 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383114 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383114 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014498 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248597 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 422216 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51148 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51148 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
|
system.iocache.overall_misses::total 173 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295925 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9596 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9596 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 117554 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 261799 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 335 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 341 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 115266 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 115266 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 82 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 435 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 842297 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 842297 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191916 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1909
|
|
system.cpu.kern.mode_good::user 1739
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|