77853b9f52
Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details.
259 lines
9.5 KiB
C++
259 lines
9.5 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sh' : ('signed int', 16),
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'uh' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'ud' : ('unsigned int', 64),
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'tud' : ('twin64 int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64)
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}};
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let {{
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maybePCRead = '''
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((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
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'''
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maybeAlignedPCRead = '''
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((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
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xc->%(func)s(this, %(op_idx)s))
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'''
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maybePCWrite = '''
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((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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maybeIWPCWrite = '''
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((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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maybeAIWPCWrite = '''
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if (%(reg_idx)s == PCReg) {
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bool thumb = THUMB;
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if (thumb) {
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setNextPC(xc, %(final_val)s);
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} else {
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setIWNextPC(xc, %(final_val)s);
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}
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} else {
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xc->%(func)s(this, %(op_idx)s, %(final_val)s);
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}
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'''
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#PCState operands need to have a sorting index (the number at the end)
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#less than all the integer registers which might update the PC. That way
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#if the flag bits of the pc state are updated and a branch happens through
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#R15, the updates are layered properly and the R15 update isn't lost.
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srtNormal = 5
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srtCpsr = 4
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srtBase = 3
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srtPC = 2
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srtMode = 1
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srtEPC = 0
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def floatReg(idx):
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return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
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def intReg(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybePCWrite)
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def intRegNPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
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def intRegAPC(idx, id = srtNormal):
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return ('IntReg', 'uw', idx, 'IsInteger', id,
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maybeAlignedPCRead, maybePCWrite)
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def intRegIWPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybeIWPCWrite)
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def intRegAIWPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybeAIWPCWrite)
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def intRegCC(idx):
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return ('IntReg', 'uw', idx, None, srtNormal)
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def cntrlReg(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
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def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, None, id)
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def pcStateReg(idx, id):
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return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
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}};
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def operands {{
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#Abstracted integer reg operands
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'Dest': intReg('dest'),
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'IWDest': intRegIWPC('dest'),
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'AIWDest': intRegAIWPC('dest'),
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'Dest2': intReg('dest2'),
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'Result': intReg('result'),
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'Base': intRegAPC('base', id = srtBase),
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'Index': intReg('index'),
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'Shift': intReg('shift'),
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'Op1': intReg('op1'),
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'Op2': intReg('op2'),
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'Op3': intReg('op3'),
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'Reg0': intReg('reg0'),
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'Reg1': intReg('reg1'),
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'Reg2': intReg('reg2'),
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'Reg3': intReg('reg3'),
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#Fixed index integer reg operands
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'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
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'LR': intRegNPC('INTREG_LR'),
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'R7': intRegNPC('7'),
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'R0': intRegNPC('0'),
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'R1': intRegNPC('0'),
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'R2': intRegNPC('1'),
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#Pseudo integer condition code registers
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'CondCodes': intRegCC('INTREG_CONDCODES'),
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'OptCondCodes': intRegCC(
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'''(condCode == COND_AL || condCode == COND_UC) ?
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INTREG_ZERO : INTREG_CONDCODES'''),
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'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
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#Abstracted floating point reg operands
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'FpDest': floatReg('(dest + 0)'),
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'FpDestP0': floatReg('(dest + 0)'),
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'FpDestP1': floatReg('(dest + 1)'),
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'FpDestP2': floatReg('(dest + 2)'),
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'FpDestP3': floatReg('(dest + 3)'),
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'FpDestP4': floatReg('(dest + 4)'),
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'FpDestP5': floatReg('(dest + 5)'),
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'FpDestP6': floatReg('(dest + 6)'),
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'FpDestP7': floatReg('(dest + 7)'),
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'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
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'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
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'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
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'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
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'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
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'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
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'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
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'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
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'FpDest2': floatReg('(dest2 + 0)'),
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'FpDest2P0': floatReg('(dest2 + 0)'),
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'FpDest2P1': floatReg('(dest2 + 1)'),
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'FpDest2P2': floatReg('(dest2 + 2)'),
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'FpDest2P3': floatReg('(dest2 + 3)'),
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'FpOp1': floatReg('(op1 + 0)'),
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'FpOp1P0': floatReg('(op1 + 0)'),
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'FpOp1P1': floatReg('(op1 + 1)'),
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'FpOp1P2': floatReg('(op1 + 2)'),
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'FpOp1P3': floatReg('(op1 + 3)'),
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'FpOp1P4': floatReg('(op1 + 4)'),
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'FpOp1P5': floatReg('(op1 + 5)'),
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'FpOp1P6': floatReg('(op1 + 6)'),
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'FpOp1P7': floatReg('(op1 + 7)'),
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'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
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'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
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'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
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'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
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'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
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'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
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'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
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'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
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'FpOp2': floatReg('(op2 + 0)'),
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'FpOp2P0': floatReg('(op2 + 0)'),
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'FpOp2P1': floatReg('(op2 + 1)'),
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'FpOp2P2': floatReg('(op2 + 2)'),
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'FpOp2P3': floatReg('(op2 + 3)'),
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#Abstracted control reg operands
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'MiscDest': cntrlReg('dest'),
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'MiscOp1': cntrlReg('op1'),
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#Fixed index control regs
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'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
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'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'),
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'Spsr': cntrlRegNC('MISCREG_SPSR'),
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'Fpsr': cntrlRegNC('MISCREG_FPSR'),
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'Fpsid': cntrlRegNC('MISCREG_FPSID'),
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'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
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'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
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'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
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'Cpacr': cntrlReg('MISCREG_CPACR'),
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'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
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'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
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'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
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#Register fields for microops
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'Ra' : intReg('ura'),
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'IWRa' : intRegIWPC('ura'),
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'Fa' : floatReg('ura'),
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'Rb' : intReg('urb'),
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'Rc' : intReg('urc'),
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
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#PCState fields
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'PC': pcStateReg('instPC', srtPC),
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'NPC': pcStateReg('instNPC', srtPC),
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'pNPC': pcStateReg('instNPC', srtEPC),
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'IWNPC': pcStateReg('instIWNPC', srtPC),
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'Thumb': pcStateReg('thumb', srtPC),
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'NextThumb': pcStateReg('nextThumb', srtMode),
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'NextJazelle': pcStateReg('nextJazelle', srtMode),
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'ForcedItState': pcStateReg('forcedItState', srtMode),
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#Register operands depending on a field in the instruction encoding. These
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#should be avoided since they may not be portable across different
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#encodings of the same instruction.
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'Rd': intReg('RD'),
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'Rm': intReg('RM'),
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'Rs': intReg('RS'),
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'Rn': intReg('RN'),
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'Rt': intReg('RT')
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}};
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