gem5/arch
Gabe Black 76daf50937 Fixed a typo.
--HG--
extra : convert_revision : 9ad2bde341a9efb2826159229427b719ff2142f4
2006-03-28 19:39:29 -05:00
..
alpha Move TLB faults into the normal Fault code. The TLB no longer fills in IPRs through its own fault() method; this is handled by the fault's invoke() methods. 2006-03-28 18:01:01 -05:00
mips support for unaligned memory access 2006-03-19 13:40:03 -05:00
sparc Fixed a typo. 2006-03-28 19:39:29 -05:00
isa_parser.py Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
isa_specific.hh Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu 2006-03-14 18:28:51 -05:00
SConscript Moved registerfile.hh to regfile.hh 2006-03-14 16:05:44 -05:00