gem5/src/python/swig
Nathan Binkert 961f8382f6 Add a function to get a SimObject's memory mode and rework
the set memory mode code to only go through the change if
it is necessary

--HG--
extra : convert_revision : 28288227bb56b0a04d756776eaf0a4ff9e1f8c20
2007-06-10 13:52:21 -07:00
..
core.i Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
debug.i Fix copyright 2006-12-21 22:41:08 -08:00
event.i Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
init.hh Fix copyright 2006-12-21 22:41:08 -08:00
pyevent.cc Pass an exception from a python event through the event queue 2007-02-17 20:27:11 -08:00
pyevent.hh Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
pyobject.cc PhysicalMemory has vector of uniform ports instead of one special one. 2007-05-19 00:24:34 -04:00
pyobject.hh Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
random.i Get rid of the Random context and add the support directly to python. 2007-02-09 16:44:02 -08:00
sim_object.i Add a function to get a SimObject's memory mode and rework 2007-06-10 13:52:21 -07:00
stats.i Do the default argument stuff in python 2007-03-03 07:45:55 -08:00
trace.i Clean up tracing stuff more, get rid of the trace log since 2007-02-10 15:14:50 -08:00