gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
Andreas Hansson 74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00

88 lines
9.3 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.006151 # Number of seconds simulated
sim_ticks 6151475 # Number of ticks simulated
final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 50702 # Simulator tick rate (ticks/s)
host_mem_usage 252748 # Number of bytes of host memory used
host_seconds 121.33 # Real time elapsed on the host
system.funcbus.throughput 0 # Throughput (bytes/s)
system.funcbus.data_through_bus 0 # Total data (bytes)
system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 76947 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76967 # Number of cache demand accesses
system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl5.L1Dcache.demand_hits 25 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 77241 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77266 # Number of cache demand accesses
system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl6.L1Dcache.demand_hits 19 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Dcache.demand_misses 77320 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77339 # Number of cache demand accesses
system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl7.L1Dcache.demand_hits 21 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Dcache.demand_misses 76925 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Dcache.demand_accesses 76946 # Number of cache demand accesses
system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Dcache.demand_hits 24 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 77267 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77291 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl1.L1Dcache.demand_hits 17 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Dcache.demand_misses 77262 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77279 # Number of cache demand accesses
system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl2.L1Dcache.demand_hits 17 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Dcache.demand_misses 77078 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77095 # Number of cache demand accesses
system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl3.L1Dcache.demand_hits 22 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Dcache.demand_misses 76783 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Dcache.demand_accesses 76805 # Number of cache demand accesses
system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_hits 1681 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 615142 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 616823 # Number of cache demand accesses
system.cpu0.num_reads 100000 # number of read accesses completed
system.cpu0.num_writes 54250 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu1.num_reads 99858 # number of read accesses completed
system.cpu1.num_writes 54337 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
system.cpu2.num_reads 99660 # number of read accesses completed
system.cpu2.num_writes 53758 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
system.cpu3.num_reads 99997 # number of read accesses completed
system.cpu3.num_writes 53569 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
system.cpu4.num_reads 99232 # number of read accesses completed
system.cpu4.num_writes 53727 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
system.cpu5.num_reads 99852 # number of read accesses completed
system.cpu5.num_writes 54401 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
system.cpu6.num_reads 99007 # number of read accesses completed
system.cpu6.num_writes 53961 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
system.cpu7.num_reads 99727 # number of read accesses completed
system.cpu7.num_writes 53437 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
---------- End Simulation Statistics ----------