74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
394 lines
45 KiB
Plaintext
394 lines
45 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000028 # Number of seconds simulated
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sim_ticks 28358000 # Number of ticks simulated
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final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 90736 # Simulator instruction rate (inst/s)
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host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 477859669 # Simulator tick rate (ticks/s)
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host_mem_usage 289160 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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sim_insts 5381 # Number of instructions simulated
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sim_ops 9748 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
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system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 814726003 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 282 # Transaction distribution
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system.membus.trans_dist::ReadResp 282 # Transaction distribution
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system.membus.trans_dist::ReadExReq 79 # Transaction distribution
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system.membus.trans_dist::ReadExResp 79 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 23104 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 56716 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 5381 # Number of instructions committed
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system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 209 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
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system.cpu.num_int_insts 9655 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 24822 # number of times the integer registers were read
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system.cpu.num_int_register_writes 11063 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 1988 # number of memory refs
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system.cpu.num_load_insts 1053 # Number of load instructions
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system.cpu.num_store_insts 935 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 56716 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use
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system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits
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system.cpu.icache.overall_hits::total 6637 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
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system.cpu.icache.overall_misses::total 228 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
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system.cpu.l2cache.overall_hits::total 1 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
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system.cpu.l2cache.overall_misses::total 361 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1854 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 134 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|