1c529a4196
All architectures execute m5 pseudo instructions by setting up arguments according to the ABI and executing a magic instruction that contains an operation number. Handling of such instructions is currently spread across the different ISA implementations. This changeset introduces the PseudoInst::pseudoInst function which handles most of this in an architecture independent way. This is function is mainly intended to be used from KVM, but can also be used from the simulated CPUs.
95 lines
4.1 KiB
C++
95 lines
4.1 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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*/
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#ifndef __SIM_PSEUDO_INST_HH__
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#define __SIM_PSEUDO_INST_HH__
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class ThreadContext;
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//We need the "Tick" and "Addr" data types from here
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#include "base/types.hh"
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namespace PseudoInst {
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/**
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* Execute a decoded M5 pseudo instruction
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*
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* The ISA-specific code is responsible to decode the pseudo inst
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* function number and subfunction number. After that has been done,
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* the rest of the instruction can be implemented in an ISA-agnostic
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* manner using the ISA-specific getArguments functions.
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*
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* @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
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* @param subfunc M5 minor function number. Mainly used for annotations.
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*/
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uint64_t pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc);
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void arm(ThreadContext *tc);
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void quiesce(ThreadContext *tc);
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void quiesceSkip(ThreadContext *tc);
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void quiesceNs(ThreadContext *tc, uint64_t ns);
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void quiesceCycles(ThreadContext *tc, uint64_t cycles);
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uint64_t quiesceTime(ThreadContext *tc);
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uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
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uint64_t offset);
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uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
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uint64_t offset, Addr filenameAddr);
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void loadsymbol(ThreadContext *xc);
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void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
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uint64_t initParam(ThreadContext *xc);
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uint64_t rpns(ThreadContext *tc);
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void wakeCPU(ThreadContext *tc, uint64_t cpuid);
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void m5exit(ThreadContext *tc, Tick delay);
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void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
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void resetstats(ThreadContext *tc, Tick delay, Tick period);
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void dumpstats(ThreadContext *tc, Tick delay, Tick period);
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void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
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void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
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void debugbreak(ThreadContext *tc);
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void switchcpu(ThreadContext *tc);
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void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
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void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
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} // namespace PseudoInst
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#endif // __SIM_PSEUDO_INST_HH__
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