589 lines
67 KiB
Text
589 lines
67 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.067367 # Number of seconds simulated
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sim_ticks 67367177000 # Number of ticks simulated
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final_tick 67367177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 124120 # Simulator instruction rate (inst/s)
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host_op_rate 218555 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 52925417 # Simulator tick rate (ticks/s)
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host_mem_usage 355732 # Number of bytes of host memory used
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host_seconds 1272.87 # Real time elapsed on the host
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sim_insts 157988582 # Number of instructions simulated
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sim_ops 278192519 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 3905024 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 69056 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 895552 # Number of bytes written to this memory
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system.physmem.num_reads 61016 # Number of read requests responded to by this memory
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system.physmem.num_writes 13993 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 57966270 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 1025069 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 13293595 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 71259866 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 444 # Number of system calls
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system.cpu.numCycles 134734355 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 36117705 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 36117705 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1086223 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 25647744 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 25539011 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 27986454 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 196428178 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 36117705 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 25539011 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 59419496 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 8404854 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 39237097 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 27269445 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 142050 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 133931620 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.578005 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.358197 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 77253594 57.68% 57.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 2167416 1.62% 59.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2996676 2.24% 61.54% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4105343 3.07% 64.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 8023701 5.99% 70.59% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 5042154 3.76% 74.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 2892095 2.16% 76.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1463696 1.09% 77.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 29986945 22.39% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 133931620 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.268066 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.457892 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 40456608 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 30121503 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 46487725 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 9577404 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 7288380 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 341192383 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 7288380 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 45850157 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 5075267 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 9166 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 50344983 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 25363667 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 337332641 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 24553 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 23217040 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 301814702 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 829797290 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 829794179 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 3111 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 53470510 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 483 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 56181617 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 108142373 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 37171875 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 46300098 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 7898843 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 331653497 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 2738 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 311383007 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 186497 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 53202508 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 70962751 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 2292 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 133931620 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.324940 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.724540 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 27909124 20.84% 20.84% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 17260254 12.89% 33.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 25571257 19.09% 52.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 31151034 23.26% 76.08% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 17658757 13.18% 89.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 9043417 6.75% 96.01% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 3762327 2.81% 98.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 1502538 1.12% 99.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 72912 0.05% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 133931620 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 23628 1.12% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1962682 92.75% 93.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 129707 6.13% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 177172854 56.90% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 149 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 99705652 32.02% 88.93% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 34472981 11.07% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 311383007 # Type of FU issued
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system.cpu.iq.rate 2.311088 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2116017 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.006796 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 758999086 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 384888890 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 308243683 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 1062 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 1674 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 367 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 313467157 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 496 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 52573681 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 17362985 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 99732 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 32451 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 5732124 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 3854 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 7288380 # Number of cycles IEW is squashing
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system.cpu.iew.iewBlockCycles 913145 # Number of cycles IEW is blocking
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system.cpu.iew.iewUnblockCycles 89980 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispatchedInsts 331656235 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispSquashedInsts 45880 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispLoadInsts 108142373 # Number of dispatched load instructions
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system.cpu.iew.iewDispStoreInsts 37171875 # Number of dispatched store instructions
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system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewIQFullEvents 1173 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewLSQFullEvents 43472 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.memOrderViolationEvents 32451 # Number of memory order violations
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system.cpu.iew.predictedTakenIncorrect 613492 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 579011 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 1192503 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecutedInsts 309419383 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 99171010 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 1963624 # Number of squashed instructions skipped in execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.exec_nop 0 # number of nop insts executed
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system.cpu.iew.exec_refs 133254790 # number of memory reference insts executed
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system.cpu.iew.exec_branches 31526578 # Number of branches executed
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system.cpu.iew.exec_stores 34083780 # Number of stores executed
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system.cpu.iew.exec_rate 2.296514 # Inst execution rate
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system.cpu.iew.wb_sent 308790761 # cumulative count of insts sent to commit
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system.cpu.iew.wb_count 308244050 # cumulative count of insts written-back
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system.cpu.iew.wb_producers 227493444 # num instructions producing a value
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system.cpu.iew.wb_consumers 314310835 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_rate 2.287791 # insts written-back per cycle
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system.cpu.iew.wb_fanout 0.723785 # average fanout of values written-back
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
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system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 53467881 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1086244 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 126643240 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.196663 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.674492 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 46336828 36.59% 36.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 24193827 19.10% 55.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 16853923 13.31% 69.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 12623187 9.97% 78.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 3354078 2.65% 81.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 3557907 2.81% 84.43% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 2707686 2.14% 86.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1157110 0.91% 87.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 15858694 12.52% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 126643240 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 157988582 # Number of instructions committed
|
|
system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 122219139 # Number of memory references committed
|
|
system.cpu.commit.loads 90779388 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 29309710 # Number of branches committed
|
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 15858694 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 442444946 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 670617818 # The number of ROB writes
|
|
system.cpu.timesIdled 23939 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 802735 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 157988582 # Number of Instructions Simulated
|
|
system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.852811 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.852811 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.172593 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.172593 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 549500021 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 275642637 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 429 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 242 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 197910962 # number of misc regfile reads
|
|
system.cpu.icache.replacements 103 # number of replacements
|
|
system.cpu.icache.tagsinuse 848.450455 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 27268036 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 24947.882891 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 848.450455 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.414282 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.414282 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 27268036 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 27268036 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 27268036 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 27268036 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 27268036 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 27268036 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1409 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1409 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1409 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1409 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1409 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1409 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50108000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 50108000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 50108000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 50108000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 50108000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 50108000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 27269445 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 27269445 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 27269445 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 27269445 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 27269445 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 27269445 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35562.810504 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35562.810504 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 315 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 315 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 315 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1094 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1094 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1094 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1094 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1094 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1094 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38230000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 38230000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38230000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 38230000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38230000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 38230000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34945.155393 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34945.155393 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 2072116 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4072.716490 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 75611002 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 2076212 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 36.417766 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 22583642000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4072.716490 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.994316 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.994316 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 44257159 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 44257159 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 31353834 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 31353834 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 75610993 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 75610993 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 75610993 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 75610993 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2289224 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2289224 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 85917 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 85917 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2375141 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2375141 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2375141 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2375141 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13801326000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 13801326000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502330294 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1502330294 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 15303656294 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 15303656294 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 15303656294 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 15303656294 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 46546383 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 46546383 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 77986134 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 77986134 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 77986134 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 77986134 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049182 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002733 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.030456 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.030456 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6028.822867 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17485.832769 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 6443.262229 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1879081 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1879081 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295092 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 295092 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3834 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3834 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 298926 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 298926 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 298926 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 298926 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994132 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1994132 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82083 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 82083 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2076215 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2076215 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2076215 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2076215 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5588966000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5588966000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158785294 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158785294 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6747751294 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6747751294 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6747751294 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6747751294 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042842 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026623 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2802.706140 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14117.238576 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3250.025308 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 33385 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 18998.818974 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3761978 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 61393 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 61.276986 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 12949.193091 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 250.074892 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 5799.550991 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.395178 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.007632 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.176988 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.579798 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1963577 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1963591 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1879081 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1879081 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 52700 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 52700 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2016277 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2016291 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2016277 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2016291 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1079 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 30422 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 31501 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 29515 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 29515 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1079 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 59937 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 61016 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1079 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 59937 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 61016 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36980000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1039210000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1076190000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006243500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1006243500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 36980000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2045453500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 2082433500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 36980000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2045453500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 2082433500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1093 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1993999 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1995092 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1879081 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1879081 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82215 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 82215 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1093 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2076214 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2077307 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1093 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2076214 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2077307 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.987191 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015257 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358998 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.987191 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.028868 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.987191 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.028868 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.474513 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34159.818552 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34092.613925 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.474513 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34126.724728 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 13993 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 13993 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30422 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 31501 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29515 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 29515 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 59937 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 61016 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 59937 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 61016 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33519500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 943737500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 977257000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915036000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915036000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33519500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1858773500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1892293000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33519500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1858773500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1892293000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015257 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358998 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987191 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028868 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.338276 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31021.546907 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.405556 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.338276 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31012.121060 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|