gem5/src
Andreas Hansson f800f268db mem: Update DDR3 and DDR4 based on datasheets
This patch makes a more firm connection between the DDR3-1600
configuration and the corresponding datasheet, and also adds a
DDR3-2133 and a DDR4-2400 configuration. At the moment there is also
an ongoing effort to align the choice of datasheets to what is
available in DRAMPower.
2014-05-09 18:58:49 -04:00
..
arch arm: Make sure UndefinedInstructions are properly initialized 2014-04-17 16:56:09 -05:00
base stats: Method stats source 2014-05-09 18:58:46 -04:00
cpu cpu: Useful getters for ActivityRecorder 2014-05-09 18:58:48 -04:00
dev dev: Set HDLCD default pixel clock for 1080p @ 60Hz 2014-05-09 18:58:46 -04:00
doc MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern sim: Add openat/fstatat syscalls and fix mremap 2014-01-24 15:29:30 -06:00
mem mem: Update DDR3 and DDR4 based on datasheets 2014-05-09 18:58:49 -04:00
proto mem: Edit proto Packet and enhance the python script 2014-03-07 15:56:23 -05:00
python cpu: Add flag name printing to StaticInst 2014-05-09 18:58:47 -04:00
sim sim, arm: implement more of the at variety syscalls 2014-04-17 16:55:05 -05:00
unittest unittest: Fix build errors 2014-01-30 12:21:58 -06:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript arch: teach ISA parser how to split code across files 2014-05-09 18:58:47 -04:00