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arm: Make sure UndefinedInstructions are properly initialized

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This commit is contained in:
Ali Saidi 2014-04-17 16:56:09 -05:00
parent a00b44ebe8
commit dbaf43394b
3 changed files with 17 additions and 12 deletions
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12
src/arch/arm/faults.hh
View file

@ -257,9 +257,9 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
{
protected:
bool unknown;
const char *mnemonic;
bool disabled;
ExceptionClass overrideEc;
const char *mnemonic;
public:
UndefinedInstruction(ExtMachInst _machInst,
@ -267,12 +267,14 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
const char *_mnemonic = NULL,
bool _disabled = false) :
ArmFaultVals<UndefinedInstruction>(_machInst),
unknown(_unknown), mnemonic(_mnemonic), disabled(_disabled),
overrideEc(EC_INVALID)
unknown(_unknown), disabled(_disabled),
overrideEc(EC_INVALID), mnemonic(_mnemonic)
{}
UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc) :
UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
overrideEc(_overrideEc)
unknown(false), disabled(true), overrideEc(_overrideEc),
mnemonic(_mnemonic)
{}
void invoke(ThreadContext *tc,

9
src/arch/arm/isa/insts/data64.isa
View file

@ -294,7 +294,8 @@ let {{
flat_idx == MISCREG_DC_CVAC_Xt ||
flat_idx == MISCREG_DC_CIVAC_Xt
)
return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
mnemonic);
return new UndefinedInstruction(machInst, false, mnemonic);
}
@ -396,7 +397,8 @@ let {{
if (!canWriteAArch64SysReg(
(MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
Scr64, Cpsr, xc->tcBase())) {
return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
mnemonic);
}
CPSR cpsr = Cpsr;
cpsr.daif = cpsr.daif | imm;
@ -407,7 +409,8 @@ let {{
if (!canWriteAArch64SysReg(
(MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
Scr64, Cpsr, xc->tcBase())) {
return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
mnemonic);
}
CPSR cpsr = Cpsr;
cpsr.daif = cpsr.daif & ~imm;

8
src/arch/arm/isa/templates/vfp.isa
View file

@ -49,7 +49,7 @@ let {{
CPSR cpsrEnCheck = Cpsr;
if (cpsrEnCheck.mode == MODE_HYP) {
return new UndefinedInstruction(machInst, issEnCheck,
EC_TRAPPED_HCPTR);
EC_TRAPPED_HCPTR, mnemonic);
} else {
if (!inSecureState(Scr, Cpsr)) {
return new HypervisorTrap(machInst, issEnCheck,
@ -96,7 +96,7 @@ let {{
CPSR cpsrEnCheck = Cpsr;
if (cpsrEnCheck.mode == MODE_HYP) {
return new UndefinedInstruction(machInst, issEnCheck,
EC_TRAPPED_HCPTR);
EC_TRAPPED_HCPTR, mnemonic);
} else {
if (!inSecureState(Scr, Cpsr)) {
return new HypervisorTrap(machInst, issEnCheck,
@ -122,7 +122,7 @@ let {{
CPSR cpsrEnCheck = Cpsr;
if (cpsrEnCheck.mode == MODE_HYP) {
return new UndefinedInstruction(machInst, issEnCheck,
EC_TRAPPED_HCPTR);
EC_TRAPPED_HCPTR, mnemonic);
} else {
if (!inSecureState(Scr, Cpsr)) {
return new HypervisorTrap(machInst, issEnCheck,
@ -142,7 +142,7 @@ let {{
CPSR cpsrEnCheck = Cpsr;
if (cpsrEnCheck.mode == MODE_HYP) {
return new UndefinedInstruction(machInst, issEnCheck,
EC_TRAPPED_HCPTR);
EC_TRAPPED_HCPTR, mnemonic);
} else {
if (!inSecureState(Scr, Cpsr)) {
return new HypervisorTrap(machInst, issEnCheck,