738 lines
31 KiB
Text
738 lines
31 KiB
Text
Real time: Jan/14/2013 22:52:15
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 462
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Elapsed_time_in_minutes: 7.7
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Elapsed_time_in_hours: 0.128333
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Elapsed_time_in_days: 0.00534722
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Virtual_time_in_seconds: 461.58
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Virtual_time_in_minutes: 7.693
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Virtual_time_in_hours: 0.128217
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Virtual_time_in_days: 0.00534236
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Ruby_current_time: 10409964586
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Ruby_start_time: 0
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Ruby_cycles: 10409964586
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mbytes_resident: 590.25
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mbytes_total: 829.625
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resident_ratio: 0.711475
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ruby_cycles_executed: [ 10409964587 10409964587 ]
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Busy Controller Counts:
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L1Cache-0:0 L1Cache-1:0
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L2Cache-0:0
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Directory-0:0
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DMA-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154388062 average: 1.00012 | standard deviation: 0.0108509 | 0 154369882 18180 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 2 max: 273 count: 154388061 average: 3.45295 | standard deviation: 5.08106 | 0 151690537 0 0 0 0 0 0 0 932040 1703 1471533 1379 91424 1420 25290 352 173 9 51 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3364 5598 7271 9474 50989 163 513 82 90 127 6 24 4 6 9 8 14 4 5 25 4 18 6 7 12 11 470 4229 10028 17505 13231 42632 784 872 2277 305 815 8 29 37 18 24 23 26 53 8 26 13 20 33 16 22 11 24 27 83 131 126 141 264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 216 count: 15287552 average: 5.10334 | standard deviation: 8.51891 | 0 13850933 0 0 0 0 0 0 0 114268 255 1245097 853 32879 910 11079 294 137 7 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 911 726 2346 2634 1956 44 90 30 21 27 1 2 1 1 2 2 4 3 3 2 2 3 5 1 1 4 0 1351 2838 4647 6042 5788 291 264 240 135 110 0 10 3 8 6 12 9 4 3 5 5 4 3 7 8 2 6 4 27 18 45 48 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 273 count: 9717504 average: 5.12149 | standard deviation: 15.1012 | 0 9364126 0 0 0 0 0 0 0 26595 28 173015 272 26742 292 2182 35 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3242 3694 6375 48918 84 398 40 60 99 3 20 3 1 7 4 9 1 1 23 2 13 0 4 10 4 468 868 2785 8639 6835 36479 336 487 1937 162 695 8 13 32 7 16 4 11 46 3 18 3 12 29 5 11 6 13 18 15 84 59 91 238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 212 count: 128175950 average: 3.11389 | standard deviation: 1.98122 | 0 127382199 0 0 0 0 0 0 0 775103 1366 1499 157 150 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1597 1530 790 33 43 20 20 6 2 0 2 2 0 4 0 1 1 0 1 0 0 2 0 2 0 2 2 1997 4318 4166 202 165 151 106 98 1 6 0 5 1 3 2 7 6 3 1 3 5 4 1 4 3 3 5 5 41 29 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read: [binsize: 2 max: 214 count: 522203 average: 6.16921 | standard deviation: 9.47561 | 0 450065 0 0 0 0 0 0 0 10577 45 32980 16 17715 77 9308 9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 83 382 379 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 68 17 113 166 3 12 2 7 2 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 342426 average: 5.64732 | standard deviation: 7.89763 | 0 300788 0 0 0 0 0 0 0 5497 9 18942 81 13938 94 2721 14 18 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 53 20 2 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5 19 36 39 34 3 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 342426 average: 3 | standard deviation: 0 | 0 0 0 342426 ]
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miss_latency_NULL: [binsize: 2 max: 273 count: 154388061 average: 3.45295 | standard deviation: 5.08106 | 0 151690537 0 0 0 0 0 0 0 932040 1703 1471533 1379 91424 1420 25290 352 173 9 51 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3364 5598 7271 9474 50989 163 513 82 90 127 6 24 4 6 9 8 14 4 5 25 4 18 6 7 12 11 470 4229 10028 17505 13231 42632 784 872 2277 305 815 8 29 37 18 24 23 26 53 8 26 13 20 33 16 22 11 24 27 83 131 126 141 264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15287552 average: 5.10334 | standard deviation: 8.51891 | 0 13850933 0 0 0 0 0 0 0 114268 255 1245097 853 32879 910 11079 294 137 7 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 911 726 2346 2634 1956 44 90 30 21 27 1 2 1 1 2 2 4 3 3 2 2 3 5 1 1 4 0 1351 2838 4647 6042 5788 291 264 240 135 110 0 10 3 8 6 12 9 4 3 5 5 4 3 7 8 2 6 4 27 18 45 48 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 2 max: 273 count: 9717504 average: 5.12149 | standard deviation: 15.1012 | 0 9364126 0 0 0 0 0 0 0 26595 28 173015 272 26742 292 2182 35 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3242 3694 6375 48918 84 398 40 60 99 3 20 3 1 7 4 9 1 1 23 2 13 0 4 10 4 468 868 2785 8639 6835 36479 336 487 1937 162 695 8 13 32 7 16 4 11 46 3 18 3 12 29 5 11 6 13 18 15 84 59 91 238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128175950 average: 3.11389 | standard deviation: 1.98122 | 0 127382199 0 0 0 0 0 0 0 775103 1366 1499 157 150 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1597 1530 790 33 43 20 20 6 2 0 2 2 0 4 0 1 1 0 1 0 0 2 0 2 0 2 2 1997 4318 4166 202 165 151 106 98 1 6 0 5 1 3 2 7 6 3 1 3 5 4 1 4 3 3 5 5 41 29 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 522203 average: 6.16921 | standard deviation: 9.47561 | 0 450065 0 0 0 0 0 0 0 10577 45 32980 16 17715 77 9308 9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 83 382 379 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 68 17 113 166 3 12 2 7 2 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 342426 average: 5.64732 | standard deviation: 7.89763 | 0 300788 0 0 0 0 0 0 0 5497 9 18942 81 13938 94 2721 14 18 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 53 20 2 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5 19 36 39 34 3 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 342426 average: 3 | standard deviation: 0 | 0 0 0 342426 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 20 count: 11148135 average: 0.604011 | standard deviation: 1.43412 | 9463752 2800 1716 2621 1672813 2611 326 245 267 831 14 9 33 96 0 0 0 0 0 0 1 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4908600 average: 0.0392664 | standard deviation: 0.391117 | 4858225 1610 1216 1960 45293 234 18 5 15 24 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 6239535 average: 1.04829 | standard deviation: 1.7624 | 4605527 1190 500 661 1627520 2377 308 240 252 807 14 9 33 96 0 0 0 0 0 0 1 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783054 average: 0.0397181 | standard deviation: 0.3938 | 4733713 1359 968 1776 44998 181 18 4 15 22 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 125546 average: 0.0220557 | standard deviation: 0.26914 | 124512 251 248 184 295 53 0 1 0 2 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 461
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system_time: 0
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page_reclaims: 142165
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 544
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Network Stats
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-------------
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total_msg_count_Control: 8609013 68872104
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total_msg_count_Request_Control: 374943 2999544
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total_msg_count_Response_Data: 8904417 641118024
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total_msg_count_Response_Control: 11255862 90046896
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total_msg_count_Writeback_Data: 4892238 352241136
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total_msg_count_Writeback_Control: 242529 1940232
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total_msgs: 34279002 total_bytes: 1157217936
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.0914405
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links_utilized_percent_switch_0_link_0: 0.0993568 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.0835242 bw: 16000 base_latency: 1
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outgoing_messages_switch_0_link_0_Request_Control: 66162 529296 [ 66162 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 2118929 152562888 [ 0 2118929 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Control: 1549489 12395912 [ 0 1549489 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 2137847 17102776 [ 2137847 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Response_Data: 60658 4367376 [ 0 60658 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Response_Control: 1598104 12784832 [ 0 28048 1570056 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 1449697 104378184 [ 1449587 110 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Control: 60538 484304 [ 60538 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.0196
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links_utilized_percent_switch_1_link_0: 0.0247412 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.0144589 bw: 16000 base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 59384 475072 [ 59384 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Data: 538601 38779272 [ 0 538601 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Control: 244316 1954528 [ 0 244316 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Control: 559677 4477416 [ 559677 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 57457 4136904 [ 0 57457 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Control: 283787 2270296 [ 0 23091 260696 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Data: 181049 13035528 [ 180829 220 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 20305 162440 [ 20305 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 0.11409
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links_utilized_percent_switch_2_link_0: 0.10253 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 0.12565 bw: 16000 base_latency: 1
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outgoing_messages_switch_2_link_0_Control: 2697524 21580192 [ 2697524 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 216185 15565320 [ 0 216185 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Control: 1945956 15567648 [ 0 115204 1830752 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Data: 1630746 117413712 [ 1630416 330 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Request_Control: 123851 990808 [ 123851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Response_Data: 2677877 192807144 [ 0 2677877 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Response_Control: 1763446 14107568 [ 0 1763446 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_3_inlinks: 2
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switch_3_outlinks: 2
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links_utilized_percent_switch_3: 0.00646039
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links_utilized_percent_switch_3_link_0: 0.00496714 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3_link_1: 0.00795363 bw: 16000 base_latency: 1
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outgoing_messages_switch_3_link_0_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Response_Data: 172147 12394584 [ 0 172147 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Response_Control: 106617 852936 [ 0 106617 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_4_inlinks: 2
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switch_4_outlinks: 2
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links_utilized_percent_switch_4: 0
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links_utilized_percent_switch_4_link_0: 0 bw: 16000 base_latency: 1
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links_utilized_percent_switch_4_link_1: 0 bw: 16000 base_latency: 1
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switch_5_inlinks: 5
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switch_5_outlinks: 5
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links_utilized_percent_switch_5: 0.0463191
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links_utilized_percent_switch_5_link_0: 0.0993568 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_1: 0.0247412 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_2: 0.10253 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_3: 0.00496714 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
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outgoing_messages_switch_5_link_0_Request_Control: 66162 529296 [ 66162 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_0_Response_Data: 2118929 152562888 [ 0 2118929 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_0_Response_Control: 1549489 12395912 [ 0 1549489 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_1_Request_Control: 59384 475072 [ 59384 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_1_Response_Data: 538601 38779272 [ 0 538601 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_1_Response_Control: 244316 1954528 [ 0 244316 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Control: 2697524 21580192 [ 2697524 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Response_Data: 216185 15565320 [ 0 216185 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Response_Control: 1945956 15567648 [ 0 115204 1830752 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Writeback_Data: 1630746 117413712 [ 1630416 330 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_3_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_3_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_3_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 519318
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 519318
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
|
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 519318 100%
|
|
|
|
Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1618529
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1618529
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.1036%
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.8964%
|
|
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1618529 100%
|
|
|
|
--- L1Cache ---
|
|
- Event Counts -
|
|
Load [11524805 3762747 ] 15287552
|
|
Ifetch [108056114 20119843 ] 128175957
|
|
Store [7679126 3245433 ] 10924559
|
|
Inv [28158 23311 ] 51469
|
|
L1_Replacement [2094944 513621 ] 2608565
|
|
Fwd_GETX [15350 14689 ] 30039
|
|
Fwd_GETS [22649 21384 ] 44033
|
|
Fwd_GET_INSTR [5 0 ] 5
|
|
Data [1528 1030 ] 2558
|
|
Data_Exclusive [1226643 92917 ] 1319560
|
|
DataS_fromL1 [21384 22654 ] 44038
|
|
Data_all_Acks [869374 422000 ] 1291374
|
|
Ack [18918 21076 ] 39994
|
|
Ack_all [20446 22106 ] 42552
|
|
WB_Ack [1510125 201134 ] 1711259
|
|
PF_Load [0 0 ] 0
|
|
PF_Ifetch [0 0 ] 0
|
|
PF_Store [0 0 ] 0
|
|
|
|
- Transitions -
|
|
NP Load [1280963 125209 ] 1406172
|
|
NP Ifetch [519207 274210 ] 793417
|
|
NP Store [295798 115226 ] 411024
|
|
NP Inv [6575 2932 ] 9507
|
|
NP L1_Replacement [0 0 ] 0
|
|
NP PF_Load [0 0 ] 0
|
|
NP PF_Ifetch [0 0 ] 0
|
|
NP PF_Store [0 0 ] 0
|
|
|
|
I Load [15537 14910 ] 30447
|
|
I Ifetch [111 223 ] 334
|
|
I Store [7313 8822 ] 16135
|
|
I Inv [0 0 ] 0
|
|
I L1_Replacement [13897 11112 ] 25009
|
|
I PF_Load [0 0 ] 0
|
|
I PF_Ifetch [0 0 ] 0
|
|
I PF_Store [0 0 ] 0
|
|
|
|
S Load [750790 485617 ] 1236407
|
|
S Ifetch [107536791 19845408 ] 127382199
|
|
S Store [18918 21077 ] 39995
|
|
S Inv [21405 20030 ] 41435
|
|
S L1_Replacement [570922 301375 ] 872297
|
|
S PF_Load [0 0 ] 0
|
|
S PF_Store [0 0 ] 0
|
|
|
|
E Load [3053717 595327 ] 3649044
|
|
E Ifetch [0 0 ] 0
|
|
E Store [120709 32410 ] 153119
|
|
E Inv [68 128 ] 196
|
|
E L1_Replacement [1104096 58886 ] 1162982
|
|
E Fwd_GETX [187 209 ] 396
|
|
E Fwd_GETS [1490 1115 ] 2605
|
|
E Fwd_GET_INSTR [1 0 ] 1
|
|
E PF_Load [0 0 ] 0
|
|
E PF_Store [0 0 ] 0
|
|
|
|
M Load [6423798 2541684 ] 8965482
|
|
M Ifetch [0 0 ] 0
|
|
M Store [7236388 3067898 ] 10304286
|
|
M Inv [110 220 ] 330
|
|
M L1_Replacement [406029 142248 ] 548277
|
|
M Fwd_GETX [15163 14480 ] 29643
|
|
M Fwd_GETS [21159 20269 ] 41428
|
|
M Fwd_GET_INSTR [4 0 ] 4
|
|
M PF_Load [0 0 ] 0
|
|
M PF_Store [0 0 ] 0
|
|
|
|
IS Load [0 0 ] 0
|
|
IS Ifetch [0 0 ] 0
|
|
IS Store [0 0 ] 0
|
|
IS Inv [0 0 ] 0
|
|
IS L1_Replacement [0 0 ] 0
|
|
IS Data_Exclusive [1226643 92917 ] 1319560
|
|
IS DataS_fromL1 [21384 22654 ] 44038
|
|
IS Data_all_Acks [567791 298981 ] 866772
|
|
IS PF_Load [0 0 ] 0
|
|
IS PF_Store [0 0 ] 0
|
|
|
|
IM Load [0 0 ] 0
|
|
IM Ifetch [0 0 ] 0
|
|
IM Store [0 0 ] 0
|
|
IM Inv [0 0 ] 0
|
|
IM L1_Replacement [0 0 ] 0
|
|
IM Data [1528 1030 ] 2558
|
|
IM Data_all_Acks [301583 123019 ] 424602
|
|
IM Ack [0 0 ] 0
|
|
IM PF_Load [0 0 ] 0
|
|
IM PF_Store [0 0 ] 0
|
|
|
|
SM Load [0 0 ] 0
|
|
SM Ifetch [0 0 ] 0
|
|
SM Store [0 0 ] 0
|
|
SM Inv [0 1 ] 1
|
|
SM L1_Replacement [0 0 ] 0
|
|
SM Ack [18918 21076 ] 39994
|
|
SM Ack_all [20446 22106 ] 42552
|
|
SM PF_Load [0 0 ] 0
|
|
SM PF_Store [0 0 ] 0
|
|
|
|
IS_I Load [0 0 ] 0
|
|
IS_I Ifetch [0 0 ] 0
|
|
IS_I Store [0 0 ] 0
|
|
IS_I Inv [0 0 ] 0
|
|
IS_I L1_Replacement [0 0 ] 0
|
|
IS_I Data_Exclusive [0 0 ] 0
|
|
IS_I DataS_fromL1 [0 0 ] 0
|
|
IS_I Data_all_Acks [0 0 ] 0
|
|
IS_I PF_Load [0 0 ] 0
|
|
IS_I PF_Store [0 0 ] 0
|
|
|
|
M_I Load [0 0 ] 0
|
|
M_I Ifetch [5 2 ] 7
|
|
M_I Store [0 0 ] 0
|
|
M_I Inv [0 0 ] 0
|
|
M_I L1_Replacement [0 0 ] 0
|
|
M_I Fwd_GETX [0 0 ] 0
|
|
M_I Fwd_GETS [0 0 ] 0
|
|
M_I Fwd_GET_INSTR [0 0 ] 0
|
|
M_I WB_Ack [1510125 201134 ] 1711259
|
|
M_I PF_Load [0 0 ] 0
|
|
M_I PF_Store [0 0 ] 0
|
|
|
|
SINK_WB_ACK Load [0 0 ] 0
|
|
SINK_WB_ACK Ifetch [0 0 ] 0
|
|
SINK_WB_ACK Store [0 0 ] 0
|
|
SINK_WB_ACK Inv [0 0 ] 0
|
|
SINK_WB_ACK L1_Replacement [0 0 ] 0
|
|
SINK_WB_ACK WB_Ack [0 0 ] 0
|
|
SINK_WB_ACK PF_Load [0 0 ] 0
|
|
SINK_WB_ACK PF_Store [0 0 ] 0
|
|
|
|
PF_IS Load [0 0 ] 0
|
|
PF_IS Ifetch [0 0 ] 0
|
|
PF_IS Store [0 0 ] 0
|
|
PF_IS Inv [0 0 ] 0
|
|
PF_IS L1_Replacement [0 0 ] 0
|
|
PF_IS Data_Exclusive [0 0 ] 0
|
|
PF_IS DataS_fromL1 [0 0 ] 0
|
|
PF_IS Data_all_Acks [0 0 ] 0
|
|
PF_IS PF_Load [0 0 ] 0
|
|
PF_IS PF_Store [0 0 ] 0
|
|
|
|
PF_IM Load [0 0 ] 0
|
|
PF_IM Ifetch [0 0 ] 0
|
|
PF_IM Store [0 0 ] 0
|
|
PF_IM Inv [0 0 ] 0
|
|
PF_IM L1_Replacement [0 0 ] 0
|
|
PF_IM Data [0 0 ] 0
|
|
PF_IM Data_all_Acks [0 0 ] 0
|
|
PF_IM Ack [0 0 ] 0
|
|
PF_IM PF_Load [0 0 ] 0
|
|
PF_IM PF_Store [0 0 ] 0
|
|
|
|
PF_SM Load [0 0 ] 0
|
|
PF_SM Ifetch [0 0 ] 0
|
|
PF_SM Store [0 0 ] 0
|
|
PF_SM Inv [0 0 ] 0
|
|
PF_SM L1_Replacement [0 0 ] 0
|
|
PF_SM Ack [0 0 ] 0
|
|
PF_SM Ack_all [0 0 ] 0
|
|
|
|
PF_IS_I Load [0 0 ] 0
|
|
PF_IS_I Store [0 0 ] 0
|
|
PF_IS_I Inv [0 0 ] 0
|
|
PF_IS_I L1_Replacement [0 0 ] 0
|
|
PF_IS_I Data_Exclusive [0 0 ] 0
|
|
PF_IS_I DataS_fromL1 [0 0 ] 0
|
|
PF_IS_I Data_all_Acks [0 0 ] 0
|
|
|
|
Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 274433
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 274433
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
|
|
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 274433 100%
|
|
|
|
Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 285244
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 285244
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 49.1225%
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 50.8775%
|
|
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 285244 100%
|
|
|
|
Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 246224
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 246224
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 30.3882%
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.26543%
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 63.346%
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.000406134%
|
|
|
|
system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 246224 100%
|
|
|
|
--- L2Cache ---
|
|
- Event Counts -
|
|
L1_GET_INSTR [793751 ] 793751
|
|
L1_GETS [1436868 ] 1436868
|
|
L1_GETX [427161 ] 427161
|
|
L1_UPGRADE [39995 ] 39995
|
|
L1_PUTX [1711259 ] 1711259
|
|
L1_PUTX_old [0 ] 0
|
|
Fwd_L1_GETX [0 ] 0
|
|
Fwd_L1_GETS [0 ] 0
|
|
Fwd_L1_GET_INSTR [0 ] 0
|
|
L2_Replacement [94211 ] 94211
|
|
L2_Replacement_clean [12406 ] 12406
|
|
Mem_Data [172147 ] 172147
|
|
Mem_Ack [106617 ] 106617
|
|
WB_Data [43746 ] 43746
|
|
WB_Data_clean [622 ] 622
|
|
Ack [1695 ] 1695
|
|
Ack_all [6892 ] 6892
|
|
Unblock [44038 ] 44038
|
|
Unblock_Cancel [0 ] 0
|
|
Exclusive_Unblock [1786714 ] 1786714
|
|
MEM_Inv [0 ] 0
|
|
|
|
- Transitions -
|
|
NP L1_GET_INSTR [15422 ] 15422
|
|
NP L1_GETS [30790 ] 30790
|
|
NP L1_GETX [125935 ] 125935
|
|
NP L1_PUTX [0 ] 0
|
|
NP L1_PUTX_old [0 ] 0
|
|
|
|
SS L1_GET_INSTR [778075 ] 778075
|
|
SS L1_GETS [73026 ] 73026
|
|
SS L1_GETX [2798 ] 2798
|
|
SS L1_UPGRADE [39994 ] 39994
|
|
SS L1_PUTX [0 ] 0
|
|
SS L1_PUTX_old [0 ] 0
|
|
SS L2_Replacement [248 ] 248
|
|
SS L2_Replacement_clean [6448 ] 6448
|
|
SS MEM_Inv [0 ] 0
|
|
|
|
M L1_GET_INSTR [249 ] 249
|
|
M L1_GETS [1288770 ] 1288770
|
|
M L1_GETX [268388 ] 268388
|
|
M L1_PUTX [0 ] 0
|
|
M L1_PUTX_old [0 ] 0
|
|
M L2_Replacement [93815 ] 93815
|
|
M L2_Replacement_clean [5580 ] 5580
|
|
M MEM_Inv [0 ] 0
|
|
|
|
MT L1_GET_INSTR [5 ] 5
|
|
MT L1_GETS [44033 ] 44033
|
|
MT L1_GETX [30039 ] 30039
|
|
MT L1_PUTX [1711259 ] 1711259
|
|
MT L1_PUTX_old [0 ] 0
|
|
MT L2_Replacement [148 ] 148
|
|
MT L2_Replacement_clean [378 ] 378
|
|
MT MEM_Inv [0 ] 0
|
|
|
|
M_I L1_GET_INSTR [0 ] 0
|
|
M_I L1_GETS [0 ] 0
|
|
M_I L1_GETX [0 ] 0
|
|
M_I L1_UPGRADE [0 ] 0
|
|
M_I L1_PUTX [0 ] 0
|
|
M_I L1_PUTX_old [0 ] 0
|
|
M_I Mem_Ack [106617 ] 106617
|
|
M_I MEM_Inv [0 ] 0
|
|
|
|
MT_I L1_GET_INSTR [0 ] 0
|
|
MT_I L1_GETS [0 ] 0
|
|
MT_I L1_GETX [0 ] 0
|
|
MT_I L1_UPGRADE [0 ] 0
|
|
MT_I L1_PUTX [0 ] 0
|
|
MT_I L1_PUTX_old [0 ] 0
|
|
MT_I WB_Data [117 ] 117
|
|
MT_I WB_Data_clean [0 ] 0
|
|
MT_I Ack_all [31 ] 31
|
|
MT_I MEM_Inv [0 ] 0
|
|
|
|
MCT_I L1_GET_INSTR [0 ] 0
|
|
MCT_I L1_GETS [0 ] 0
|
|
MCT_I L1_GETX [0 ] 0
|
|
MCT_I L1_UPGRADE [0 ] 0
|
|
MCT_I L1_PUTX [0 ] 0
|
|
MCT_I L1_PUTX_old [0 ] 0
|
|
MCT_I WB_Data [213 ] 213
|
|
MCT_I WB_Data_clean [0 ] 0
|
|
MCT_I Ack_all [165 ] 165
|
|
|
|
I_I L1_GET_INSTR [0 ] 0
|
|
I_I L1_GETS [0 ] 0
|
|
I_I L1_GETX [0 ] 0
|
|
I_I L1_UPGRADE [0 ] 0
|
|
I_I L1_PUTX [0 ] 0
|
|
I_I L1_PUTX_old [0 ] 0
|
|
I_I Ack [1454 ] 1454
|
|
I_I Ack_all [6448 ] 6448
|
|
|
|
S_I L1_GET_INSTR [0 ] 0
|
|
S_I L1_GETS [0 ] 0
|
|
S_I L1_GETX [0 ] 0
|
|
S_I L1_UPGRADE [0 ] 0
|
|
S_I L1_PUTX [0 ] 0
|
|
S_I L1_PUTX_old [0 ] 0
|
|
S_I Ack [241 ] 241
|
|
S_I Ack_all [248 ] 248
|
|
S_I MEM_Inv [0 ] 0
|
|
|
|
ISS L1_GET_INSTR [0 ] 0
|
|
ISS L1_GETS [0 ] 0
|
|
ISS L1_GETX [0 ] 0
|
|
ISS L1_PUTX [0 ] 0
|
|
ISS L1_PUTX_old [0 ] 0
|
|
ISS L2_Replacement [0 ] 0
|
|
ISS L2_Replacement_clean [0 ] 0
|
|
ISS Mem_Data [30790 ] 30790
|
|
ISS MEM_Inv [0 ] 0
|
|
|
|
IS L1_GET_INSTR [0 ] 0
|
|
IS L1_GETS [0 ] 0
|
|
IS L1_GETX [0 ] 0
|
|
IS L1_PUTX [0 ] 0
|
|
IS L1_PUTX_old [0 ] 0
|
|
IS L2_Replacement [0 ] 0
|
|
IS L2_Replacement_clean [0 ] 0
|
|
IS Mem_Data [15422 ] 15422
|
|
IS MEM_Inv [0 ] 0
|
|
|
|
IM L1_GET_INSTR [0 ] 0
|
|
IM L1_GETS [0 ] 0
|
|
IM L1_GETX [0 ] 0
|
|
IM L1_PUTX [0 ] 0
|
|
IM L1_PUTX_old [0 ] 0
|
|
IM L2_Replacement [0 ] 0
|
|
IM L2_Replacement_clean [0 ] 0
|
|
IM Mem_Data [125935 ] 125935
|
|
IM MEM_Inv [0 ] 0
|
|
|
|
SS_MB L1_GET_INSTR [0 ] 0
|
|
SS_MB L1_GETS [193 ] 193
|
|
SS_MB L1_GETX [0 ] 0
|
|
SS_MB L1_UPGRADE [1 ] 1
|
|
SS_MB L1_PUTX [0 ] 0
|
|
SS_MB L1_PUTX_old [0 ] 0
|
|
SS_MB L2_Replacement [0 ] 0
|
|
SS_MB L2_Replacement_clean [0 ] 0
|
|
SS_MB Unblock_Cancel [0 ] 0
|
|
SS_MB Exclusive_Unblock [42792 ] 42792
|
|
SS_MB MEM_Inv [0 ] 0
|
|
|
|
MT_MB L1_GET_INSTR [0 ] 0
|
|
MT_MB L1_GETS [56 ] 56
|
|
MT_MB L1_GETX [1 ] 1
|
|
MT_MB L1_UPGRADE [0 ] 0
|
|
MT_MB L1_PUTX [0 ] 0
|
|
MT_MB L1_PUTX_old [0 ] 0
|
|
MT_MB L2_Replacement [0 ] 0
|
|
MT_MB L2_Replacement_clean [0 ] 0
|
|
MT_MB Unblock_Cancel [0 ] 0
|
|
MT_MB Exclusive_Unblock [1743922 ] 1743922
|
|
MT_MB MEM_Inv [0 ] 0
|
|
|
|
M_MB L1_GET_INSTR [0 ] 0
|
|
M_MB L1_GETS [0 ] 0
|
|
M_MB L1_GETX [0 ] 0
|
|
M_MB L1_UPGRADE [0 ] 0
|
|
M_MB L1_PUTX [0 ] 0
|
|
M_MB L1_PUTX_old [0 ] 0
|
|
M_MB L2_Replacement [0 ] 0
|
|
M_MB L2_Replacement_clean [0 ] 0
|
|
M_MB Exclusive_Unblock [0 ] 0
|
|
M_MB MEM_Inv [0 ] 0
|
|
|
|
MT_IIB L1_GET_INSTR [0 ] 0
|
|
MT_IIB L1_GETS [0 ] 0
|
|
MT_IIB L1_GETX [0 ] 0
|
|
MT_IIB L1_UPGRADE [0 ] 0
|
|
MT_IIB L1_PUTX [0 ] 0
|
|
MT_IIB L1_PUTX_old [0 ] 0
|
|
MT_IIB L2_Replacement [0 ] 0
|
|
MT_IIB L2_Replacement_clean [0 ] 0
|
|
MT_IIB WB_Data [43375 ] 43375
|
|
MT_IIB WB_Data_clean [622 ] 622
|
|
MT_IIB Unblock [41 ] 41
|
|
MT_IIB MEM_Inv [0 ] 0
|
|
|
|
MT_IB L1_GET_INSTR [0 ] 0
|
|
MT_IB L1_GETS [0 ] 0
|
|
MT_IB L1_GETX [0 ] 0
|
|
MT_IB L1_UPGRADE [0 ] 0
|
|
MT_IB L1_PUTX [0 ] 0
|
|
MT_IB L1_PUTX_old [0 ] 0
|
|
MT_IB L2_Replacement [0 ] 0
|
|
MT_IB L2_Replacement_clean [0 ] 0
|
|
MT_IB WB_Data [41 ] 41
|
|
MT_IB WB_Data_clean [0 ] 0
|
|
MT_IB Unblock_Cancel [0 ] 0
|
|
MT_IB MEM_Inv [0 ] 0
|
|
|
|
MT_SB L1_GET_INSTR [0 ] 0
|
|
MT_SB L1_GETS [0 ] 0
|
|
MT_SB L1_GETX [0 ] 0
|
|
MT_SB L1_UPGRADE [0 ] 0
|
|
MT_SB L1_PUTX [0 ] 0
|
|
MT_SB L1_PUTX_old [0 ] 0
|
|
MT_SB L2_Replacement [0 ] 0
|
|
MT_SB L2_Replacement_clean [0 ] 0
|
|
MT_SB Unblock [43997 ] 43997
|
|
MT_SB MEM_Inv [0 ] 0
|
|
|
|
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 266571
|
|
memory_reads: 172147
|
|
memory_writes: 94424
|
|
memory_refreshes: 536635
|
|
memory_total_request_delays: 1016562
|
|
memory_delays_per_request: 3.81348
|
|
memory_delays_in_input_queue: 40063
|
|
memory_delays_behind_head_of_bank_queue: 7489
|
|
memory_delays_stalled_at_head_of_bank_queue: 969010
|
|
memory_stalls_for_bank_busy: 959685
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 0
|
|
memory_stalls_for_arbitration: 2157
|
|
memory_stalls_for_bus: 7147
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 15
|
|
memory_stalls_for_read_read_turnaround: 6
|
|
accesses_per_bank: 8989 7974 8010 8055 8487 8273 8235 8188 8380 8237 8148 8446 8268 8048 8068 7184 8265 8304 8191 8114 8382 8281 8178 8162 8416 8296 8511 9107 9086 9056 8973 8259
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
Fetch [172147 ] 172147
|
|
Data [94424 ] 94424
|
|
Memory_Data [172147 ] 172147
|
|
Memory_Ack [94424 ] 94424
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
CleanReplacement [12193 ] 12193
|
|
|
|
- Transitions -
|
|
I Fetch [172147 ] 172147
|
|
I DMA_READ [0 ] 0
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
ID Fetch [0 ] 0
|
|
ID Data [0 ] 0
|
|
ID Memory_Data [0 ] 0
|
|
ID DMA_READ [0 ] 0
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
ID_W Fetch [0 ] 0
|
|
ID_W Data [0 ] 0
|
|
ID_W Memory_Ack [0 ] 0
|
|
ID_W DMA_READ [0 ] 0
|
|
ID_W DMA_WRITE [0 ] 0
|
|
|
|
M Data [94424 ] 94424
|
|
M DMA_READ [0 ] 0
|
|
M DMA_WRITE [0 ] 0
|
|
M CleanReplacement [12193 ] 12193
|
|
|
|
IM Fetch [0 ] 0
|
|
IM Data [0 ] 0
|
|
IM Memory_Data [172147 ] 172147
|
|
IM DMA_READ [0 ] 0
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
MI Fetch [0 ] 0
|
|
MI Data [0 ] 0
|
|
MI Memory_Ack [94424 ] 94424
|
|
MI DMA_READ [0 ] 0
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
M_DRD Data [0 ] 0
|
|
M_DRD DMA_READ [0 ] 0
|
|
M_DRD DMA_WRITE [0 ] 0
|
|
|
|
M_DRDI Fetch [0 ] 0
|
|
M_DRDI Data [0 ] 0
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
M_DRDI DMA_READ [0 ] 0
|
|
M_DRDI DMA_WRITE [0 ] 0
|
|
|
|
M_DWR Data [0 ] 0
|
|
M_DWR DMA_READ [0 ] 0
|
|
M_DWR DMA_WRITE [0 ] 0
|
|
|
|
M_DWRI Fetch [0 ] 0
|
|
M_DWRI Data [0 ] 0
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
M_DWRI DMA_READ [0 ] 0
|
|
M_DWRI DMA_WRITE [0 ] 0
|
|
|
|
--- DMA ---
|
|
- Event Counts -
|
|
ReadRequest [0 ] 0
|
|
WriteRequest [0 ] 0
|
|
Data [0 ] 0
|
|
Ack [0 ] 0
|
|
|
|
- Transitions -
|
|
READY ReadRequest [0 ] 0
|
|
READY WriteRequest [0 ] 0
|
|
|
|
BUSY_RD Data [0 ] 0
|
|
|
|
BUSY_WR Ack [0 ] 0
|
|
|