46f6fa8b45
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.out:
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout:
Update refs.
--HG--
extra : convert_revision : 34a0d18f213386700e2acdd1eb9ebc5fa6daa7f5
405 lines
43 KiB
Text
405 lines
43 KiB
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 3154 # Number of BTB hits
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global.BPredUnit.BTBLookups 9574 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted
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global.BPredUnit.lookups 10459 # Number of BP lookups
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global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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host_inst_rate 26468 # Simulator instruction rate (inst/s)
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host_mem_usage 154944 # Number of bytes of host memory used
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host_seconds 0.41 # Real time elapsed on the host
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host_tick_rate 32157366 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 10976 # Number of instructions simulated
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sim_seconds 0.000013 # Number of seconds simulated
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sim_ticks 13345500 # Number of ticks simulated
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system.cpu.commit.COM:branches 2152 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 23147
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 17950 7754.78%
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1 2912 1258.05%
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2 993 429.00%
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3 424 183.18%
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4 287 123.99%
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5 235 101.53%
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6 103 44.50%
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7 79 34.13%
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8 164 70.85%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 10976 # Number of instructions committed
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system.cpu.commit.COM:loads 1462 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 2760 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 10976 # Number of Instructions Simulated
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system.cpu.committedInsts_total 10976 # Number of Instructions Simulated
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system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
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system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 3824 # number of overall hits
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system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 281 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use
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system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched
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system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 26692
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system.cpu.fetch.rateDist.min_value 0
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0 15871 5945.98%
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1 2250 842.95%
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2 637 238.65%
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3 971 363.78%
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4 550 206.05%
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5 848 317.70%
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6 962 360.41%
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7 321 120.26%
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8 4282 1604.23%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency
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system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses
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system.cpu.icache.demand_misses 380 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 5060 # number of overall hits
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system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses
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system.cpu.icache.overall_misses 380 # number of overall misses
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system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use
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system.cpu.icache.total_refs 5060 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.iew.EXEC:branches 3713 # Number of branches executed
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system.cpu.iew.EXEC:nop 0 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate
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system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 2589 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 10966 # num instructions consuming a value
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system.cpu.iew.WB:count 21367 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 8771 # num instructions producing a value
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system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle
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system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
(null) 1919 7.50% # Type of FU issued
|
|
IntAlu 17231 67.33% # Type of FU issued
|
|
IntMult 0 0.00% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 3429 13.40% # Type of FU issued
|
|
MemWrite 3014 11.78% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
IntAlu 99 41.60% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 22 9.24% # attempts to use FU when none available
|
|
MemWrite 117 49.16% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 26692
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 17644 6610.22%
|
|
1 3262 1222.09%
|
|
2 1371 513.64%
|
|
3 1071 401.24%
|
|
4 1568 587.44%
|
|
5 925 346.55%
|
|
6 579 216.92%
|
|
7 171 64.06%
|
|
8 101 37.84%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 526 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 26692 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|