13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
440 lines
49 KiB
Text
440 lines
49 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 221900 # Simulator instruction rate (inst/s)
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host_mem_usage 202972 # Number of bytes of host memory used
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host_seconds 358.68 # Real time elapsed on the host
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host_tick_rate 75369122 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 79591756 # Number of instructions simulated
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sim_seconds 0.027034 # Number of seconds simulated
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sim_ticks 27033689000 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 8073345 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 14152511 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 36189 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 458905 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 10574319 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 16281513 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1942543 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 13754477 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 3315405 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 51596234 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.712153 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.330354 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 22410479 43.43% 43.43% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 11292136 21.89% 65.32% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 5122096 9.93% 75.25% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 3547417 6.88% 82.12% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 2566622 4.97% 87.10% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 1508057 2.92% 90.02% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 1006074 1.95% 91.97% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 827948 1.60% 93.57% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 3315405 6.43% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 51596234 # Number of insts commited each cycle
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system.cpu.commit.COM:count 88340672 # Number of instructions committed
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system.cpu.commit.COM:loads 20379399 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 35224018 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 362306 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 8339248 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 79591756 # Number of Instructions Simulated
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system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
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system.cpu.cpi 0.679309 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.679309 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 20462752 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 30131.608065 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20434.335315 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 20316340 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4411629000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007155 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 146412 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 84834 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1258305500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.003009 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 61578 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 31003.810080 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32919.803194 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 13581378 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 31995900999 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.070620 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1031999 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 888502 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 4723892999 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.009820 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 143497 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 165.294463 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 35076129 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 30895.443100 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 33897718 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 36407529999 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.033596 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1178411 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 973336 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 5982198499 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005847 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 205075 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.995480 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4077.485052 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 35076129 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 30895.443100 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 33897718 # number of overall hits
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system.cpu.dcache.overall_miss_latency 36407529999 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.033596 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1178411 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 973336 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 5982198499 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005847 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 205075 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 200979 # number of replacements
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system.cpu.dcache.sampled_refs 205075 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4077.485052 # Cycle average of tags in use
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system.cpu.dcache.total_refs 33897762 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 181365000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 161485 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 3372983 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 97431 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3660168 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 101877731 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 28530714 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 19554245 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1300005 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 281200 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 138292 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 36642762 # DTB accesses
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system.cpu.dtb.data_acv 38 # DTB access violations
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system.cpu.dtb.data_hits 36466941 # DTB hits
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system.cpu.dtb.data_misses 175821 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 21568925 # DTB read accesses
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system.cpu.dtb.read_acv 36 # DTB read access violations
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system.cpu.dtb.read_hits 21411469 # DTB read hits
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system.cpu.dtb.read_misses 157456 # DTB read misses
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system.cpu.dtb.write_accesses 15073837 # DTB write accesses
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system.cpu.dtb.write_acv 2 # DTB write access violations
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system.cpu.dtb.write_hits 15055472 # DTB write hits
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system.cpu.dtb.write_misses 18365 # DTB write misses
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system.cpu.fetch.Branches 16281513 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 13394440 # Number of cache lines fetched
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system.cpu.fetch.Cycles 33285984 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 153835 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 103456008 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 576870 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.301134 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 13394440 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 10015888 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.913464 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 52896239 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.955829 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.944816 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 33031612 62.45% 62.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1863332 3.52% 65.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1548849 2.93% 68.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 1858475 3.51% 72.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 3937136 7.44% 79.85% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1852242 3.50% 83.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 690247 1.30% 84.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1146451 2.17% 86.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 6967895 13.17% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 52896239 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 13394440 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 9549.980865 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 6051.228388 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 13305596 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 848458500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.006633 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 88844 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 2837 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 520448000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.006421 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 86007 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 154.705439 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 13394440 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 9549.980865 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency
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system.cpu.icache.demand_hits 13305596 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 848458500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.006633 # miss rate for demand accesses
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system.cpu.icache.demand_misses 88844 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 2837 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 520448000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.006421 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 86007 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.936980 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 1918.935161 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 13394440 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 9549.980865 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 13305596 # number of overall hits
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system.cpu.icache.overall_miss_latency 848458500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.006633 # miss rate for overall accesses
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system.cpu.icache.overall_misses 88844 # number of overall misses
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system.cpu.icache.overall_mshr_hits 2837 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 520448000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.006421 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 86007 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 83959 # number of replacements
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system.cpu.icache.sampled_refs 86006 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1918.935161 # Cycle average of tags in use
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system.cpu.icache.total_refs 13305596 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 1171140 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 14765953 # Number of branches executed
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system.cpu.iew.EXEC:nop 9399098 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.570651 # Inst execution rate
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system.cpu.iew.EXEC:refs 36985556 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 15306955 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 42195611 # num instructions consuming a value
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system.cpu.iew.WB:count 84441959 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.765718 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 32309953 # num instructions producing a value
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system.cpu.iew.WB:rate 1.561791 # insts written-back per cycle
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system.cpu.iew.WB:sent 84679067 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 403539 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 558736 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 23014663 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 5005 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 344896 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 16344120 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 99062445 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 21678601 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 539249 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 84921008 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 9867 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 8786 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1300005 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 41358 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 947297 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 703 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 20504 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1356 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 2635264 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1499501 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 20504 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 133144 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 270395 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 1.472085 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.472085 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47958643 56.12% 56.12% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 42972 0.05% 56.17% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122098 0.14% 56.31% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122222 0.14% 56.45% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.45% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38519 0.05% 56.50% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 21787306 25.49% 81.99% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388360 18.01% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 85460257 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 970619 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011358 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 98326 10.13% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.13% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 436344 44.96% 55.09% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 435949 44.91% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 52896239 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.615621 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720411 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 17480622 33.05% 33.05% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 13990970 26.45% 59.50% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 8059116 15.24% 74.73% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 4840128 9.15% 83.88% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 4581404 8.66% 92.54% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 2086569 3.94% 96.49% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 1156021 2.19% 98.67% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 475188 0.90% 99.57% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 226221 0.43% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 52896239 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 1.580625 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 89658342 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 85460257 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 9847468 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 48230 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 422 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 6786581 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 13421357 # ITB accesses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_hits 13394440 # ITB hits
|
|
system.cpu.itb.fetch_misses 26917 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 143498 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34310.090850 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31208.995937 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_hits 12072 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_miss_latency 4509238000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.915873 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 131426 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4101673500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915873 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 131426 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 147584 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.410943 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.923979 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 103938 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 1489830500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.295737 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 43646 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1354463000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295737 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 43646 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 161485 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 161485 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.759972 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 291082 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34266.293296 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 116010 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 5999068500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.601453 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 175072 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 5456136500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.601453 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 175072 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_%::0 0.094631 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_%::1 0.481096 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_blocks::0 3100.873906 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 15764.562961 # Average occupied blocks per context
|
|
system.cpu.l2cache.overall_accesses 291082 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34266.293296 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 116010 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 5999068500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.601453 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 175072 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 5456136500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.601453 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 175072 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 148714 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 174071 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 18865.436867 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 132289 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 120514 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 12522416 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11202183 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 23014663 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 16344120 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 54067379 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 1899423 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 50756 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 28921656 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1270692 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 121761220 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 101056260 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 60792051 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 19304913 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1300005 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 1392613 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 8245170 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 77629 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 5282 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 2690297 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 5280 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 40629 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|