393 lines
14 KiB
C++
393 lines
14 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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* Ali Saidi
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*/
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/process.hh"
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#include "arch/arm/types.hh"
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#include "base/loader/elf_object.hh"
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#include "base/loader/object_file.hh"
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#include "base/misc.hh"
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#include "cpu/thread_context.hh"
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#include "mem/page_table.hh"
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#include "mem/translating_port.hh"
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#include "sim/byteswap.hh"
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#include "sim/process_impl.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace ArmISA;
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ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile,
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ObjectFile::Arch _arch)
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: LiveProcess(params, objFile), arch(_arch)
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{
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stack_base = 0xbf000000L;
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// Set pointer for next thread stack. Reserve 8M for main stack.
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next_thread_stack_base = stack_base - (8 * 1024 * 1024);
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// Set up break point (Top of Heap)
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brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
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brk_point = roundUp(brk_point, VMPageSize);
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// Set up region for mmaps. For now, start at bottom of kuseg space.
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mmap_start = mmap_end = 0x40000000L;
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}
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void
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ArmLiveProcess::startup()
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{
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LiveProcess::startup();
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argsInit(MachineBytes, VMPageSize);
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for (int i = 0; i < contextIds.size(); i++) {
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ThreadContext * tc = system->getThreadContext(contextIds[i]);
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CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
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// Enable the floating point coprocessors.
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cpacr.cp10 = 0x3;
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cpacr.cp11 = 0x3;
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tc->setMiscReg(MISCREG_CPACR, cpacr);
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// Generically enable floating point support.
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FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
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fpexc.en = 1;
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tc->setMiscReg(MISCREG_FPEXC, fpexc);
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}
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}
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void
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ArmLiveProcess::argsInit(int intSize, int pageSize)
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{
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typedef AuxVector<uint32_t> auxv_t;
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std::vector<auxv_t> auxv;
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string filename;
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if (argv.size() < 1)
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filename = "";
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else
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filename = argv[0];
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//We want 16 byte alignment
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uint64_t align = 16;
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// load object file into target memory
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objFile->loadSections(initVirtMem);
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enum ArmCpuFeature {
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Arm_Swp = 1 << 0,
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Arm_Half = 1 << 1,
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Arm_Thumb = 1 << 2,
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Arm_26Bit = 1 << 3,
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Arm_FastMult = 1 << 4,
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Arm_Fpa = 1 << 5,
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Arm_Vfp = 1 << 6,
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Arm_Edsp = 1 << 7,
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Arm_Java = 1 << 8,
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Arm_Iwmmxt = 1 << 9,
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Arm_Crunch = 1 << 10,
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Arm_ThumbEE = 1 << 11,
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Arm_Neon = 1 << 12,
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Arm_Vfpv3 = 1 << 13,
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Arm_Vfpv3d16 = 1 << 14
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};
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//Setup the auxilliary vectors. These will already have endian conversion.
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//Auxilliary vectors are loaded only for elf formatted executables.
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ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
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if (elfObject) {
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uint32_t features =
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Arm_Swp |
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Arm_Half |
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Arm_Thumb |
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// Arm_26Bit |
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Arm_FastMult |
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// Arm_Fpa |
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Arm_Vfp |
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Arm_Edsp |
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// Arm_Java |
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// Arm_Iwmmxt |
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// Arm_Crunch |
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Arm_ThumbEE |
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Arm_Neon |
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Arm_Vfpv3 |
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Arm_Vfpv3d16 |
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0;
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//Bits which describe the system hardware capabilities
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//XXX Figure out what these should be
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auxv.push_back(auxv_t(M5_AT_HWCAP, features));
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//The system page size
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auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize));
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//Frequency at which times() increments
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auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
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// For statically linked executables, this is the virtual address of the
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// program header tables if they appear in the executable image
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auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
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// This is the size of a program header entry from the elf file.
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auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
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// This is the number of program headers from the original elf file.
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auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
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//This is the address of the elf "interpreter", It should be set
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//to 0 for regular executables. It should be something else
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//(not sure what) for dynamic libraries.
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auxv.push_back(auxv_t(M5_AT_BASE, 0));
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//XXX Figure out what this should be.
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auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
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//The entry point to the program
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auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
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//Different user and group IDs
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auxv.push_back(auxv_t(M5_AT_UID, uid()));
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auxv.push_back(auxv_t(M5_AT_EUID, euid()));
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auxv.push_back(auxv_t(M5_AT_GID, gid()));
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auxv.push_back(auxv_t(M5_AT_EGID, egid()));
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//Whether to enable "secure mode" in the executable
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auxv.push_back(auxv_t(M5_AT_SECURE, 0));
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// Pointer to 16 bytes of random data
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auxv.push_back(auxv_t(M5_AT_RANDOM, 0));
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//The filename of the program
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auxv.push_back(auxv_t(M5_AT_EXECFN, 0));
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//The string "v71" -- ARM v7 architecture
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auxv.push_back(auxv_t(M5_AT_PLATFORM, 0));
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}
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//Figure out how big the initial stack nedes to be
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// A sentry NULL void pointer at the top of the stack.
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int sentry_size = intSize;
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string platform = "v71";
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int platform_size = platform.size() + 1;
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// Bytes for AT_RANDOM above, we'll just keep them 0
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int aux_random_size = 16; // as per the specification
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// The aux vectors are put on the stack in two groups. The first group are
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// the vectors that are generated as the elf is loaded. The second group
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// are the ones that were computed ahead of time and include the platform
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// string.
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int aux_data_size = filename.size() + 1;
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int env_data_size = 0;
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for (int i = 0; i < envp.size(); ++i) {
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env_data_size += envp[i].size() + 1;
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}
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int arg_data_size = 0;
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for (int i = 0; i < argv.size(); ++i) {
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arg_data_size += argv[i].size() + 1;
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}
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int info_block_size =
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sentry_size + env_data_size + arg_data_size +
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aux_data_size + platform_size + aux_random_size;
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//Each auxilliary vector is two 4 byte words
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int aux_array_size = intSize * 2 * (auxv.size() + 1);
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int envp_array_size = intSize * (envp.size() + 1);
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int argv_array_size = intSize * (argv.size() + 1);
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int argc_size = intSize;
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//Figure out the size of the contents of the actual initial frame
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int frame_size =
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info_block_size +
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aux_array_size +
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envp_array_size +
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argv_array_size +
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argc_size;
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//There needs to be padding after the auxiliary vector data so that the
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//very bottom of the stack is aligned properly.
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int partial_size = frame_size;
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int aligned_partial_size = roundUp(partial_size, align);
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int aux_padding = aligned_partial_size - partial_size;
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int space_needed = frame_size + aux_padding;
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stack_min = stack_base - space_needed;
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stack_min = roundDown(stack_min, align);
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stack_size = stack_base - stack_min;
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// map memory
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pTable->allocate(roundDown(stack_min, pageSize),
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roundUp(stack_size, pageSize));
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// map out initial stack contents
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uint32_t sentry_base = stack_base - sentry_size;
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uint32_t aux_data_base = sentry_base - aux_data_size;
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uint32_t env_data_base = aux_data_base - env_data_size;
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uint32_t arg_data_base = env_data_base - arg_data_size;
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uint32_t platform_base = arg_data_base - platform_size;
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uint32_t aux_random_base = platform_base - aux_random_size;
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uint32_t auxv_array_base = aux_random_base - aux_array_size - aux_padding;
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uint32_t envp_array_base = auxv_array_base - envp_array_size;
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uint32_t argv_array_base = envp_array_base - argv_array_size;
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uint32_t argc_base = argv_array_base - argc_size;
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DPRINTF(Stack, "The addresses of items on the initial stack:\n");
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DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
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DPRINTF(Stack, "0x%x - env data\n", env_data_base);
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DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
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DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
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DPRINTF(Stack, "0x%x - platform base\n", platform_base);
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DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
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DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
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DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
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DPRINTF(Stack, "0x%x - argc \n", argc_base);
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DPRINTF(Stack, "0x%x - stack min\n", stack_min);
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// write contents to stack
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// figure out argc
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uint32_t argc = argv.size();
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uint32_t guestArgc = ArmISA::htog(argc);
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//Write out the sentry void *
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uint32_t sentry_NULL = 0;
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initVirtMem->writeBlob(sentry_base,
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(uint8_t*)&sentry_NULL, sentry_size);
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//Fix up the aux vectors which point to other data
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for (int i = auxv.size() - 1; i >= 0; i--) {
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if (auxv[i].a_type == M5_AT_PLATFORM) {
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auxv[i].a_val = platform_base;
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initVirtMem->writeString(platform_base, platform.c_str());
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} else if (auxv[i].a_type == M5_AT_EXECFN) {
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auxv[i].a_val = aux_data_base;
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initVirtMem->writeString(aux_data_base, filename.c_str());
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} else if (auxv[i].a_type == M5_AT_RANDOM) {
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auxv[i].a_val = aux_random_base;
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// Just leave the value 0, we don't want randomness
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}
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}
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//Copy the aux stuff
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for(int x = 0; x < auxv.size(); x++)
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{
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initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
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(uint8_t*)&(auxv[x].a_type), intSize);
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initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
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(uint8_t*)&(auxv[x].a_val), intSize);
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}
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//Write out the terminating zeroed auxilliary vector
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const uint64_t zero = 0;
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initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
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(uint8_t*)&zero, 2 * intSize);
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copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
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copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
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initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
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ThreadContext *tc = system->getThreadContext(contextIds[0]);
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//Set the stack pointer register
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tc->setIntReg(StackPointerReg, stack_min);
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//A pointer to a function to run when the program exits. We'll set this
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//to zero explicitly to make sure this isn't used.
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tc->setIntReg(ArgumentReg0, 0);
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//Set argument regs 1 and 2 to argv[0] and envp[0] respectively
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if (argv.size() > 0) {
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tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
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argv[argv.size() - 1].size() - 1);
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} else {
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tc->setIntReg(ArgumentReg1, 0);
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}
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if (envp.size() > 0) {
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tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
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envp[envp.size() - 1].size() - 1);
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} else {
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tc->setIntReg(ArgumentReg2, 0);
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}
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PCState pc;
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pc.thumb(arch == ObjectFile::Thumb);
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pc.nextThumb(pc.thumb());
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pc.set(objFile->entryPoint() & ~mask(1));
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tc->pcState(pc);
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//Align the "stack_min" to a page boundary.
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stack_min = roundDown(stack_min, pageSize);
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}
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ArmISA::IntReg
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ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
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{
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assert(i < 6);
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return tc->readIntReg(ArgumentReg0 + i++);
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}
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uint64_t
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ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i, int width)
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{
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assert(width == 32 || width == 64);
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if (width == 32)
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return getSyscallArg(tc, i);
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// 64 bit arguments are passed starting in an even register
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if (i % 2 != 0)
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i++;
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// Registers r0-r6 can be used
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assert(i < 5);
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uint64_t val;
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val = tc->readIntReg(ArgumentReg0 + i++);
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val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
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return val;
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}
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void
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ArmLiveProcess::setSyscallArg(ThreadContext *tc,
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int i, ArmISA::IntReg val)
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{
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assert(i < 4);
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tc->setIntReg(ArgumentReg0 + i, val);
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}
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void
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ArmLiveProcess::setSyscallReturn(ThreadContext *tc,
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SyscallReturn return_value)
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{
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tc->setIntReg(ReturnValueReg, return_value.value());
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}
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