Gabe Black 6db65b40c1 Arm: Add in a missing miscRegName.		2011-03-25 00:46:14 -04:00
..
alpha	O3: Send instruction back to fetch on squash to seed predecoder correctly.	2011-03-17 19:20:19 -05:00
arm	Arm: Add in a missing miscRegName.	2011-03-25 00:46:14 -04:00
generic	X86: Define fault objects to carry debug messages.	2011-02-13 17:42:05 -08:00
mips	O3: Send instruction back to fetch on squash to seed predecoder correctly.	2011-03-17 19:20:19 -05:00
noisa	SCons: Support building without an ISA	2010-11-19 18:00:39 -06:00
power	O3: Send instruction back to fetch on squash to seed predecoder correctly.	2011-03-17 19:20:19 -05:00
sparc	O3: Send instruction back to fetch on squash to seed predecoder correctly.	2011-03-17 19:20:19 -05:00
x86	O3: Send instruction back to fetch on squash to seed predecoder correctly.	2011-03-17 19:20:19 -05:00
isa_parser.py	ISA parser: Set up op_src_decl and op_dest_decl for pc operands.	2011-03-24 13:55:16 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	Spelling: Fix the a spelling error by changing mmaped to mmapped.	2011-03-01 23:18:47 -08:00