205 lines
6.9 KiB
C++
205 lines
6.9 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_ARM_ISA_HH__
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#include "arch/arm/registers.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/types.hh"
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class ThreadContext;
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA
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{
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protected:
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MiscReg miscRegs[NumMiscRegs];
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const IntRegIndex *intRegMap;
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void
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updateRegMap(CPSR cpsr)
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{
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switch (cpsr.mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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intRegMap = IntRegUsrMap;
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break;
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case MODE_FIQ:
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intRegMap = IntRegFiqMap;
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break;
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case MODE_IRQ:
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intRegMap = IntRegIrqMap;
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break;
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case MODE_SVC:
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intRegMap = IntRegSvcMap;
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break;
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case MODE_MON:
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intRegMap = IntRegMonMap;
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break;
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case MODE_ABORT:
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intRegMap = IntRegAbtMap;
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break;
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case MODE_UNDEFINED:
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intRegMap = IntRegUndMap;
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break;
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default:
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panic("Unrecognized mode setting in CPSR.\n");
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}
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}
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public:
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void clear();
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MiscReg readMiscRegNoEffect(int misc_reg);
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MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
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int
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flattenIntIndex(int reg)
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{
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assert(reg >= 0);
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if (reg < NUM_ARCH_INTREGS) {
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return intRegMap[reg];
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} else if (reg < NUM_INTREGS) {
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return reg;
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} else {
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int mode = reg / intRegsPerMode;
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reg = reg % intRegsPerMode;
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switch (mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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return INTREG_USR(reg);
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case MODE_FIQ:
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return INTREG_FIQ(reg);
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case MODE_IRQ:
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return INTREG_IRQ(reg);
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case MODE_SVC:
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return INTREG_SVC(reg);
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case MODE_MON:
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return INTREG_MON(reg);
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case MODE_ABORT:
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return INTREG_ABT(reg);
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case MODE_UNDEFINED:
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return INTREG_UND(reg);
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default:
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panic("Flattening into an unknown mode.\n");
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}
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}
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}
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int
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flattenFloatIndex(int reg)
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{
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return reg;
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}
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int
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flattenMiscIndex(int reg)
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{
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if (reg == MISCREG_SPSR) {
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int spsr_idx = NUM_MISCREGS;
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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warn("User mode does not have SPSR\n");
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spsr_idx = MISCREG_SPSR;
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break;
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case MODE_FIQ:
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spsr_idx = MISCREG_SPSR_FIQ;
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break;
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case MODE_IRQ:
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spsr_idx = MISCREG_SPSR_IRQ;
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break;
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case MODE_SVC:
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spsr_idx = MISCREG_SPSR_SVC;
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break;
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case MODE_MON:
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spsr_idx = MISCREG_SPSR_MON;
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break;
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case MODE_ABORT:
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spsr_idx = MISCREG_SPSR_ABT;
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break;
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case MODE_UNDEFINED:
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spsr_idx = MISCREG_SPSR_UND;
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break;
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default:
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warn("Trying to access SPSR in an invalid mode: %d\n",
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cpsr.mode);
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spsr_idx = MISCREG_SPSR;
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break;
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}
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return spsr_idx;
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}
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return reg;
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}
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void serialize(EventManager *em, std::ostream &os)
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{
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DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
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SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
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}
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void unserialize(EventManager *em, Checkpoint *cp,
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const std::string §ion)
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{
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DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
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UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
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CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
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updateRegMap(tmp_cpsr);
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}
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ISA()
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{
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SCTLR sctlr;
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sctlr = 0;
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miscRegs[MISCREG_SCTLR_RST] = sctlr;
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clear();
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}
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};
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}
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#endif
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